semihosting: move semihosting cmd to arm cmd group
Move semihosting cmd to the arm cmd group. Targets that support semihosting will setup the setup_semihosting callback function. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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@ -6021,6 +6021,18 @@ Display a table of all banked core registers, fetching the current value from ev
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core mode if necessary.
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@end deffn
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@deffn Command {arm semihosting} [@option{enable}|@option{disable}]
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@cindex ARM semihosting
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Display status of semihosting, after optionally changing that status.
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Semihosting allows for code executing on an ARM target to use the
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I/O facilities on the host computer i.e. the system where OpenOCD
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is running. The target application must be linked against a library
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implementing the ARM semihosting convention that forwards operation
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requests by using a special SVC instruction that is trapped at the
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Supervisor Call vector by OpenOCD.
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@end deffn
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@section ARMv4 and ARMv5 Architecture
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@cindex ARMv4
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@cindex ARMv5
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@ -6073,18 +6085,6 @@ cables (FT2232), but might be unsafe if used with targets running at very low
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speeds, like the 32kHz startup clock of an AT91RM9200.
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@end deffn
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@deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
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@cindex ARM semihosting
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Display status of semihosting, after optionally changing that status.
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Semihosting allows for code executing on an ARM target to use the
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I/O facilities on the host computer i.e. the system where OpenOCD
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is running. The target application must be linked against a library
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implementing the ARM semihosting convention that forwards operation
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requests by using a special SVC instruction that is trapped at the
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Supervisor Call vector by OpenOCD.
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@end deffn
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@subsection ARM720T specific commands
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@cindex ARM720T
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@ -132,6 +132,8 @@ struct arm {
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/** Value to be returned by semihosting SYS_ERRNO request. */
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int semihosting_errno;
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int (*setup_semihosting)(struct target *target, int enable);
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/** Backpointer to the target. */
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struct target *target;
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@ -2834,54 +2834,32 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_arm7_9_semihosting_command)
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int arm7_9_setup_semihosting(struct target *target, int enable)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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if (!is_arm7_9(arm7_9))
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{
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command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
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LOG_USER("current target isn't an ARM7/ARM9 target");
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return ERROR_TARGET_INVALID;
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}
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if (CMD_ARGC > 0)
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{
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int semihosting;
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COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
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if (!target_was_examined(target))
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{
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LOG_ERROR("Target not examined yet");
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return ERROR_FAIL;
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}
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if (arm7_9->has_vector_catch) {
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struct reg *vector_catch = &arm7_9->eice_cache
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->reg_list[EICE_VEC_CATCH];
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if (!vector_catch->valid)
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embeddedice_read_reg(vector_catch);
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buf_set_u32(vector_catch->value, 2, 1, semihosting);
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embeddedice_store_reg(vector_catch);
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} else {
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/* TODO: allow optional high vectors and/or BKPT_HARD */
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if (semihosting)
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breakpoint_add(target, 8, 4, BKPT_SOFT);
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else
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breakpoint_remove(target, 8);
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}
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/* FIXME never let that "catch" be dropped! */
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arm7_9->armv4_5_common.is_semihosting = semihosting;
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if (arm7_9->has_vector_catch) {
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struct reg *vector_catch = &arm7_9->eice_cache
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->reg_list[EICE_VEC_CATCH];
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if (!vector_catch->valid)
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embeddedice_read_reg(vector_catch);
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buf_set_u32(vector_catch->value, 2, 1, enable);
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embeddedice_store_reg(vector_catch);
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} else {
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/* TODO: allow optional high vectors and/or BKPT_HARD */
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if (enable)
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breakpoint_add(target, 8, 4, BKPT_SOFT);
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else
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breakpoint_remove(target, 8);
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}
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command_print(CMD_CTX, "semihosting is %s",
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arm7_9->armv4_5_common.is_semihosting
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? "enabled" : "disabled");
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return ERROR_OK;
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}
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@ -2906,6 +2884,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
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armv4_5->read_core_reg = arm7_9_read_core_reg;
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armv4_5->write_core_reg = arm7_9_write_core_reg;
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armv4_5->full_context = arm7_9_full_context;
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armv4_5->setup_semihosting = arm7_9_setup_semihosting;
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retval = arm_init_arch_info(target, armv4_5);
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if (retval != ERROR_OK)
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@ -2939,13 +2918,6 @@ static const struct command_registration arm7_9_any_command_handlers[] = {
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.usage = "['enable'|'disable']",
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.help = "use DCC downloads for larger memory writes",
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},
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{
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"semihosting",
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.handler = handle_arm7_9_semihosting_command,
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.mode = COMMAND_EXEC,
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.usage = "['enable'|'disable']",
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.help = "activate support for semihosting operations",
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},
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COMMAND_REGISTRATION_DONE
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};
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const struct command_registration arm7_9_command_handlers[] = {
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@ -951,6 +951,49 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
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return JIM_OK;
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}
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COMMAND_HANDLER(handle_arm_semihosting_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct arm *arm = target ? target_to_arm(target) : NULL;
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if (!is_arm(arm)) {
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command_print(CMD_CTX, "current target isn't an ARM");
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return ERROR_FAIL;
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}
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if (!arm->setup_semihosting)
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{
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command_print(CMD_CTX, "semihosting not supported for current target");
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}
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if (CMD_ARGC > 0)
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{
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int semihosting;
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COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
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if (!target_was_examined(target))
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{
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LOG_ERROR("Target not examined yet");
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return ERROR_FAIL;
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}
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if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
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LOG_ERROR("Failed to Configure semihosting");
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return ERROR_FAIL;
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}
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/* FIXME never let that "catch" be dropped! */
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arm->is_semihosting = semihosting;
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}
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command_print(CMD_CTX, "semihosting is %s",
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arm->is_semihosting
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? "enabled" : "disabled");
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return ERROR_OK;
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}
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static const struct command_registration arm_exec_command_handlers[] = {
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{
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.name = "reg",
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@ -985,6 +1028,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
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.help = "read coprocessor register",
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.usage = "cpnum op1 CRn op2 CRm",
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},
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{
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"semihosting",
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.handler = handle_arm_semihosting_command,
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.mode = COMMAND_EXEC,
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.usage = "['enable'|'disable']",
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.help = "activate support for semihosting operations",
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},
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COMMAND_REGISTRATION_DONE
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};
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