Commit Graph

11322 Commits

Author SHA1 Message Date
Tim Newsome 54372dd5a6
Merge pull request #908 from MarekVCodasip/disable-soft-bp-size-2-non-compressed
target/riscv: Reject size 2 soft breakpoints when C extension not supported
2023-09-07 10:03:36 -07:00
Marek Vrbka 8ad41767c0 target/riscv: Reject size 2 soft breakpoints when C extension not supported
This patch disables software breakpoints of size 2 for targets
which don't support compressed instructions.

Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04 07:47:03 +02:00
Tim Newsome 699eecaab4
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
2023-08-30 10:59:54 -07:00
Tim Newsome 5efea16944
Merge pull request #900 from aap-sc/aap-sc/simplify_state_managment
riscv: simplify state management during examine
2023-08-29 10:11:52 -07:00
Marek Vrbka 0b914fe5ae target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-25 07:54:59 +02:00
Tim Newsome 928f2b374a
Merge pull request #904 from kr-sc/kr-sc/support-sv57
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23 12:03:21 -07:00
Tim Newsome 7aedb15951
Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_running
fix crash when we try to read vector register on a running target
2023-08-23 12:01:49 -07:00
Tim Newsome 5cb60e3f7d
Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
2023-08-18 09:32:51 -07:00
Parshintsev Anatoly 198edca6d0 riscv: simplify state management during examine
This also fixes a bug when, after `examine` completion, the target still
has  `unknown` status. To reproduce this one spike, it is enough to do
the following:

---
// make sure spike harts are halted
openocd ... -c init -c 'echo "[targets]"'
---

this behavior is quite dangerous and leads to segfaults in some cases

Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 15:29:19 +03:00
Parshintsev Anatoly 0ae47ae472 fix crash when we try to read vector register on a running target
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 00:18:10 +03:00
Tim Newsome f061623568
Merge pull request #901 from aap-sc/aap-sc/refactor_reg_rw_progbuf
[riscv] refactor functions that register read/write via progbuf
2023-08-17 09:27:28 -07:00
Xiang W 373b8f1a89 target/riscv: fix execute_fence
This patch improves the following issues:
1. Makes it compatible with targets with progbufsize == 1.
2. Although exceptions don’t update any registers, but  do end execution
of the progbuf. This will make fence rw, rw impossible to execute.

Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6
Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-17 09:05:36 +08:00
Parshintsev Anatoly a8fedebcb4 [riscv] refactor functions that register read/write via progbuf
The motivation for this refactor is to fixup error handling for some
corner cases. These functions attempt to cache S0 register and only then
perform a bunch of extra checks to figure out if the requested register
is valid one in this context. The problem is that there are few corner
cases when _*progbuf functions could receive a GPR as an input. For
example, an abstract read could fail (for whatever reason) leading to
infinite recursion:

````
save S0 -> read S0 -> save S0 -> read S0 -> ...
```

The case described above could be fixed by adding extra sanitity checks,
however I decided to make these functions more modular since I find
self-contained functions easier to read.

Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-15 17:54:00 +03:00
Tim Newsome 9260101307
Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlbl
target/riscv: improve error handling in trigger setup
2023-08-14 09:48:03 -07:00
Tim Newsome 68ad364f27
Merge pull request #897 from aap-sc/aap-sc/wp_data_not_implemented
add diagnostics for non-implemented data watchpoints
2023-08-14 09:43:24 -07:00
Kirill Radkin 1d2eea0399 target/riscv: Add support for Sv57 translation mode (including second-stage translations)
Also fix Sv48x4 translation mode
2023-08-14 14:33:44 +03:00
Evgeniy Naydanov 9b558838b1 target/riscv: improve error handling in trigger setup
Change-Id: I235973a3c44fb3d934925c74ffee47f8bd96de0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-08-03 17:58:16 +03:00
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Tim Newsome ee5c5c292f
Merge pull request #895 from kr-sc/kr-sc/reset-fails-with-assert
target/riscv: OpenOCD fails with assert during running "reset" command
2023-08-01 09:10:41 -07:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Tim Newsome 1997e68dcb
Merge pull request #875 from zqb-all/support_multiple_DMs
target/riscv: support multiple DMs
2023-07-27 08:44:34 -07:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Tim Newsome aeb37cb461
Merge pull request #882 from MarekVCodasip/target-logging-usage
target/riscv: Add target name logging to most log prints.
2023-07-24 08:59:06 -07:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Tim Newsome 21fd3e1d6c
Merge pull request #885 from erhankur/fix_tool_warnings
Fix Checkpatch and Sparse tool warnings
2023-07-21 09:12:55 -07:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Erhan Kurubas e6f30aef80 src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-20 23:09:06 +02:00
Tim Newsome 1a089d8409
Merge pull request #888 from MarekVCodasip/ci-run-spike64-if-spike32-failed
github/ci Make Spike64-2 tests run regardless of Spike32 tests result
2023-07-20 12:09:20 -07:00
Tim Newsome c1cce47933
Merge pull request #886 from erhankur/update_espressif_chips
Update espressif chips
2023-07-20 12:06:59 -07:00
Tim Newsome fba957ab8e
Merge pull request #891 from riscv/cache_master
Run spike tests on `riscv` branch.
2023-07-19 11:15:29 -07:00
Erhan Kurubas 79bcab76a0 tcl/board: add Espressif board configs with builtin usb jtag
Board config files, to allow communication with
the builtin USB-JTAG adapter.

Change-Id: I80fb0c36b3cc164940ff266f1eaa287d870da94d
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19 00:11:47 +02:00
Erhan Kurubas f21bd77dd1 tcl/target: add Espressif riscv targets (ESP32-C6, ESP32-H2)
ESP32-C6 and ESP32-H2 are single core riscv targets.

Change-Id: If92429de4fb67a040f303a54177d61b70e1ea281
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19 00:11:42 +02:00
Erhan Kurubas c7500f9161 tcl/target: update esp32c2.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Change-Id: I825dd4fddb88e5514429d49ab13869ee6b9a28fc
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19 00:11:37 +02:00
Erhan Kurubas cd36a25865 tcl/target: update esp32c3.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie3413d3149388b17bc0199409ce86d3eb7cf5ee2
2023-07-19 00:11:33 +02:00
Erhan Kurubas 28446139da tcl/board: add esp32s3-builtin.cfg file
Board config file for ESP32-S3, to allow communication with
the builtin USB-JTAG adapter.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1310f5db30f7df38fe9344f7ba2334611b53863e
Reviewed-on: https://review.openocd.org/c/openocd/+/7749
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-19 00:11:28 +02:00
Erhan Kurubas 5d78bc8ba6 tcl/interface: add Espressif builtin usb_jtag config file.
This config file enables communication over USB-JTAG with
ESP32-C3, ESP32-S3, ESP32-H2 and ESP32-C6 chips

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iceea26972588d8c4919d1f3248684ece48ca9121
Reviewed-on: https://review.openocd.org/c/openocd/+/7748
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:11:22 +02:00
Erhan Kurubas ab2618d557 tcl/target: update esp32s3.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:11:17 +02:00
Erhan Kurubas 01612de6ce tcl/target: update esp32s2.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0
Reviewed-on: https://review.openocd.org/c/openocd/+/7746
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:11:12 +02:00
Erhan Kurubas faf67b9e12 tcl/target: update esp32.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7745
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-19 00:10:57 +02:00
Erhan Kurubas d64f490f22 tcl/target: move Espressif shared functions to esp_common.cfg
Consolidate commonly used commands and variables from
chip config files into functions in esp_common.cfg.
This includes "jtag newtap," "target create,"and "configure -event."
Enhances code reusability and simplifies maintenance.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70
Reviewed-on: https://review.openocd.org/c/openocd/+/7744
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:10:35 +02:00
Tim Newsome ee0a8605ea Run spike tests on `riscv` branch.
The main reason is to populate the cache, so that pull requests can
benefit from a spike cache even the very first time. (Caches populated
in one pull request are inaccessible to another one.)

Change-Id: If894f2ccfaadc740bd52e34be3024153626b9fbd
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-18 11:08:17 -07:00
Tim Newsome fb284475a8
Merge pull request #878 from en-sc/en-sc/trigg-eq-check
target/riscv: cleanup trigger setup
2023-07-18 09:32:37 -07:00
Marek Vrbka deb0d918e2 github/ci Make Spike64-2 tests run regardless if Spike32 tests result
This patch separates the Spike tests into their own jobs and makes them run
regardless of the results of the previous test. Previously, if Spike32
tests failed, Spike64-2 tests did not even run. This can be an issue if new
tests are added in the riscv-tests repository which are not yet passing
on riscv-openocd.

Change-Id: I0bdaee5fbbba5582babab40f176cfab49660c246
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-18 14:48:31 +02:00
Evgeniy Naydanov a8f28fdd48 target/riscv: cleanup trigger setup
* Add a warning when eq trigger is setup and it's behavior is different
from other triggers.

* Make eq trigger's behavior consistent with other triggers in case of
length == 1.

* Fix a bug in setting chained triggers (LT, GT case).

* Improve logging.

Change-Id: Id1ed0d11971b8ed875afbb979e6c8a8b51dd3818
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-17 20:41:01 +03:00
Tim Newsome b67b80c6ac
Merge pull request #879 from riscv/power_dance3
target/breakpoints: Clear software breakpoints from available targets
2023-07-17 09:30:41 -07:00
Tim Newsome 814a3b5e7b
Merge pull request #871 from en-sc/en-sc/fix-mdx-err
target/riscv: refactor read_memory_progbuf()
2023-07-17 09:30:11 -07:00
Evgeniy Naydanov 8d660ea98d target/riscv: refactor read_memory_progbuf()
There were a couple of problems with previous implementation:

* Misalligned read would return ERROR_OK and print all zeroes.

* CMDERR_BUSY for abstract access was improperly handled:

According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.

* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.

Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-14 22:23:02 +03:00