Merge pull request #885 from erhankur/fix_tool_warnings
Fix Checkpatch and Sparse tool warnings
This commit is contained in:
Tim Newsome
GitHub
commit
21fd3e1d6c
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@ -3012,7 +3012,8 @@ static int gdb_query_packet(struct connection *connection,
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return ERROR_OK;
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}
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static bool gdb_handle_vcont_packet(struct connection *connection, const char *packet, int packet_size)
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static bool gdb_handle_vcont_packet(struct connection *connection, const char *packet,
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__attribute__((unused)) int packet_size)
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{
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struct gdb_connection *gdb_connection = connection->priv;
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struct target *target = get_available_target_from_connection(connection);
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@ -3031,7 +3032,6 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
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if (parse[0] == ';') {
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++parse;
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--packet_size;
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}
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/* simple case, a continue packet */
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@ -3070,14 +3070,11 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
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int current_pc = 1;
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int64_t thread_id;
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parse++;
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packet_size--;
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if (parse[0] == ':') {
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char *endp;
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parse++;
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packet_size--;
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thread_id = strtoll(parse, &endp, 16);
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if (endp) {
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packet_size -= endp - parse;
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parse = endp;
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}
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} else {
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@ -3115,7 +3112,6 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
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if (parse[0] == ';') {
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++parse;
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--packet_size;
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if (parse[0] == 'c') {
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parse += 1;
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@ -1553,7 +1553,6 @@ static int arm7_9_restore_context(struct target *target)
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if (dirty) {
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uint32_t mask = 0x0;
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int num_regs = 0;
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uint32_t regs[16];
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if (mode_change) {
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@ -1576,7 +1575,6 @@ static int arm7_9_restore_context(struct target *target)
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if (reg->dirty) {
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regs[j] = buf_get_u32(reg->value, 0, 32);
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mask |= 1 << j;
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num_regs++;
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reg->dirty = false;
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reg->valid = true;
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LOG_DEBUG("writing register %i mode %s "
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@ -127,7 +127,7 @@ int riscv_batch_run(struct riscv_batch *batch)
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return ERROR_OK;
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}
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void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data,
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void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data,
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bool read_back)
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{
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assert(batch->used_scans < batch->allocated_scans);
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@ -194,7 +194,7 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
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batch->used_scans++;
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}
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void dump_field(int idle, const struct scan_field *field)
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static void dump_field(int idle, const struct scan_field *field)
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{
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static const char * const op_string[] = {"-", "r", "w", "?"};
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static const char * const status_string[] = {"+", "?", "F", "b"};
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@ -59,7 +59,7 @@ bool riscv_batch_full(struct riscv_batch *batch);
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int riscv_batch_run(struct riscv_batch *batch);
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/* Adds a DMI write to this batch. */
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void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data,
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void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data,
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bool read_back);
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/* DMI reads must be handled in two parts: the first one schedules a read and
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@ -47,9 +47,9 @@ static int riscv013_step_current_hart(struct target *target);
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static int riscv013_on_step(struct target *target);
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static int riscv013_resume_prep(struct target *target);
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static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
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static int riscv013_write_debug_buffer(struct target *target, unsigned index,
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static int riscv013_write_debug_buffer(struct target *target, unsigned int index,
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riscv_insn_t d);
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static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned
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static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int
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index);
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static int riscv013_invalidate_cached_debug_buffer(struct target *target);
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static int riscv013_execute_debug_buffer(struct target *target);
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@ -1005,7 +1005,7 @@ static uint32_t abstract_memory_size(unsigned width)
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* Creates a memory access abstract command.
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*/
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static uint32_t access_memory_command(struct target *target, bool virtual,
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unsigned width, bool postincrement, bool is_write)
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unsigned int width, bool postincrement, bool is_write)
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{
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uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
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command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
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@ -1855,8 +1855,8 @@ static int examine(struct target *target)
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if (!halted) {
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r->prepped = true;
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if (riscv013_halt_go(target) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during examine()",
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info->index);
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LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during %s",
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info->index, __func__);
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return ERROR_FAIL;
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}
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target->state = TARGET_HALTED;
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@ -4104,35 +4104,35 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
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uint32_t sbvalue[4] = { 0 };
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if (size > 12) {
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sbvalue[3] = ((uint32_t) p[12]) |
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(((uint32_t) p[13]) << 8) |
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(((uint32_t) p[14]) << 16) |
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(((uint32_t) p[15]) << 24);
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sbvalue[3] = ((uint32_t)p[12]) |
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(((uint32_t)p[13]) << 8) |
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(((uint32_t)p[14]) << 16) |
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(((uint32_t)p[15]) << 24);
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riscv_batch_add_dmi_write(batch, DM_SBDATA3, sbvalue[3], false);
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}
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if (size > 8) {
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sbvalue[2] = ((uint32_t) p[8]) |
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(((uint32_t) p[9]) << 8) |
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(((uint32_t) p[10]) << 16) |
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(((uint32_t) p[11]) << 24);
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sbvalue[2] = ((uint32_t)p[8]) |
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(((uint32_t)p[9]) << 8) |
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(((uint32_t)p[10]) << 16) |
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(((uint32_t)p[11]) << 24);
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riscv_batch_add_dmi_write(batch, DM_SBDATA2, sbvalue[2], false);
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}
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if (size > 4) {
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sbvalue[1] = ((uint32_t) p[4]) |
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(((uint32_t) p[5]) << 8) |
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(((uint32_t) p[6]) << 16) |
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(((uint32_t) p[7]) << 24);
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sbvalue[1] = ((uint32_t)p[4]) |
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(((uint32_t)p[5]) << 8) |
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(((uint32_t)p[6]) << 16) |
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(((uint32_t)p[7]) << 24);
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riscv_batch_add_dmi_write(batch, DM_SBDATA1, sbvalue[1], false);
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}
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sbvalue[0] = p[0];
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if (size > 2) {
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sbvalue[0] |= ((uint32_t) p[2]) << 16;
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sbvalue[0] |= ((uint32_t) p[3]) << 24;
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sbvalue[0] |= ((uint32_t)p[2]) << 16;
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sbvalue[0] |= ((uint32_t)p[3]) << 24;
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}
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if (size > 1)
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sbvalue[0] |= ((uint32_t) p[1]) << 8;
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sbvalue[0] |= ((uint32_t)p[1]) << 8;
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riscv_batch_add_dmi_write(batch, DM_SBDATA0, sbvalue[0], false);
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@ -4595,7 +4595,7 @@ static int select_prepped_harts(struct target *target)
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struct target *t = entry->target;
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struct riscv_info *info = riscv_info(t);
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riscv013_info_t *info_013 = get_info(t);
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unsigned index = info_013->index;
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unsigned int index = info_013->index;
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LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, info->prepped);
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if (info->prepped) {
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info_013->selected = true;
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@ -4779,11 +4779,11 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
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}
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LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
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LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t) dcsr);
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LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t)dcsr);
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return RISCV_HALT_UNKNOWN;
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}
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int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
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static int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t data)
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{
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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@ -4798,14 +4798,14 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins
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return ERROR_OK;
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}
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riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index)
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static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index)
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{
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uint32_t value;
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dmi_read(target, &value, DM_PROGBUF0 + index);
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return value;
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}
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int riscv013_invalidate_cached_debug_buffer(struct target *target)
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static int riscv013_invalidate_cached_debug_buffer(struct target *target)
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{
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dm013_info_t *dm = get_dm(target);
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if (!dm) {
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@ -4819,7 +4819,7 @@ int riscv013_invalidate_cached_debug_buffer(struct target *target)
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return ERROR_OK;
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}
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int riscv013_execute_debug_buffer(struct target *target)
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static int riscv013_execute_debug_buffer(struct target *target)
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{
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uint32_t run_program = 0;
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run_program = set_field(run_program, AC_ACCESS_REGISTER_AARSIZE, 2);
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@ -4830,7 +4830,7 @@ int riscv013_execute_debug_buffer(struct target *target)
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return execute_abstract_command(target, run_program);
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}
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void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
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static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
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{
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RISCV013_INFO(info);
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buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
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@ -4838,7 +4838,7 @@ void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64
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buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
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}
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void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
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static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
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{
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RISCV013_INFO(info);
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buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
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@ -4846,7 +4846,7 @@ void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
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buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
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}
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void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
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static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
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{
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RISCV013_INFO(info);
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buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
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@ -4854,7 +4854,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
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buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
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}
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int riscv013_dmi_write_u64_bits(struct target *target)
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static int riscv013_dmi_write_u64_bits(struct target *target)
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{
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RISCV013_INFO(info);
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return info->abits + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH;
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@ -4933,7 +4933,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
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return ERROR_FAIL;
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}
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void riscv013_clear_abstract_error(struct target *target)
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static void riscv013_clear_abstract_error(struct target *target)
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{
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/* Wait for busy to go away. */
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time_t start = time(NULL);
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@ -28,7 +28,7 @@
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#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
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#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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#define field_value(mask, val) set_field((riscv_reg_t) 0, mask, val)
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#define field_value(mask, val) set_field((riscv_reg_t)0, mask, val)
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/*** JTAG registers. ***/
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@ -516,9 +516,9 @@ static bool can_use_napot_match(struct trigger *trigger)
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{
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riscv_reg_t addr = trigger->address;
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riscv_reg_t size = trigger->length;
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bool sizePowerOf2 = (size & (size - 1)) == 0;
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bool addrAligned = (addr & (size - 1)) == 0;
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return size > 1 && sizePowerOf2 && addrAligned;
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bool size_power_of_2 = (size & (size - 1)) == 0;
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bool addr_aligned = (addr & (size - 1)) == 0;
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return size > 1 && size_power_of_2 && addr_aligned;
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}
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/* Find the next free trigger of the given type, without talking to the target. */
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@ -531,7 +531,7 @@ static int find_next_free_trigger(struct target *target, int type, bool chained,
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unsigned int num_found = 0;
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unsigned int num_required = chained ? 2 : 1;
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for (unsigned i = *idx; i < r->trigger_count; i++) {
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for (unsigned int i = *idx; i < r->trigger_count; i++) {
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if (r->trigger_unique_id[i] == -1) {
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if (r->trigger_tinfo[i] & (1 << type)) {
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num_found++;
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@ -561,7 +561,7 @@ static int find_first_trigger_by_id(struct target *target, int unique_id)
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{
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RISCV_INFO(r);
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for (unsigned i = 0; i < r->trigger_count; i++) {
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for (unsigned int i = 0; i < r->trigger_count; i++) {
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if (r->trigger_unique_id[i] == unique_id)
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return i;
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}
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@ -760,8 +760,8 @@ struct match_triggers_tdata1_fields {
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riscv_reg_t tdata1_ignore_mask;
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};
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static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
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struct target *target, struct trigger *trigger)
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static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(struct target *target,
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struct trigger *trigger)
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{
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RISCV_INFO(r);
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@ -796,8 +796,8 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
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return result;
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}
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static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(
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struct target *target, struct trigger *trigger)
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static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(struct target *target,
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struct trigger *trigger)
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{
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bool misa_s = riscv_supports_extension(target, 'S');
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bool misa_u = riscv_supports_extension(target, 'U');
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@ -1578,7 +1578,7 @@ int riscv_flush_registers(struct target *target)
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/**
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* Set OpenOCD's generic debug reason from the RISC-V halt reason.
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*/
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int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
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static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
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{
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RISCV_INFO(r);
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r->trigger_hit = -1;
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@ -2684,7 +2684,7 @@ static int riscv_checksum_memory(struct target *target,
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buf_set_u64(reg_params[1].value, 0, xlen, count);
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/* 20 second timeout/megabyte */
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int timeout = 20000 * (1 + (count / (1024 * 1024)));
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unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
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retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
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crc_algorithm->address,
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@ -2913,10 +2913,10 @@ int riscv_openocd_poll(struct target *target)
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targets = &single_target_list;
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}
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unsigned should_remain_halted = 0;
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unsigned should_resume = 0;
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unsigned halted = 0;
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unsigned running = 0;
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unsigned int should_remain_halted = 0;
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unsigned int should_resume = 0;
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unsigned int halted = 0;
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unsigned int running = 0;
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struct target_list *entry;
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foreach_smp_target(entry, targets) {
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struct target *t = entry->target;
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@ -3509,9 +3509,9 @@ COMMAND_HANDLER(riscv_dmi_write)
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- if debug module was reset, in which case progbuf registers
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may not retain their value.
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*/
|
||||
bool progbufTouched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
|
||||
bool dmDeactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
|
||||
if (progbufTouched || dmDeactivated) {
|
||||
bool progbuf_touched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
|
||||
bool dm_deactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
|
||||
if (progbuf_touched || dm_deactivated) {
|
||||
if (r->invalidate_cached_debug_buffer)
|
||||
r->invalidate_cached_debug_buffer(target);
|
||||
}
|
||||
|
|
@ -3949,7 +3949,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
|
|||
|
||||
if (CMD_ARGC == 0) {
|
||||
command_print(CMD, "Memory sample configuration for %s:", target_name(target));
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
|
||||
for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
|
||||
if (r->sample_config.bucket[i].enabled) {
|
||||
command_print(CMD, "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d", i,
|
||||
r->sample_config.bucket[i].address,
|
||||
|
|
@ -3969,7 +3969,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
|
|||
uint32_t bucket;
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket);
|
||||
if (bucket > ARRAY_SIZE(r->sample_config.bucket)) {
|
||||
LOG_ERROR("Max bucket number is %d.", (unsigned) ARRAY_SIZE(r->sample_config.bucket));
|
||||
LOG_ERROR("Max bucket number is %zu.", ARRAY_SIZE(r->sample_config.bucket));
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
|
|
@ -4036,7 +4036,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
|
|||
command_print(CMD, "%s", encoded);
|
||||
free(encoded);
|
||||
} else {
|
||||
unsigned i = 0;
|
||||
unsigned int i = 0;
|
||||
while (i < r->sample_buf.used) {
|
||||
uint8_t command = r->sample_buf.buf[i++];
|
||||
if (command == RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE) {
|
||||
|
|
@ -4080,7 +4080,7 @@ error:
|
|||
}
|
||||
|
||||
COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
|
||||
unsigned value)
|
||||
unsigned int value)
|
||||
{
|
||||
char full_key[80];
|
||||
snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
|
||||
|
|
@ -4437,7 +4437,7 @@ static const struct command_registration riscv_command_handlers[] = {
|
|||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
static unsigned riscv_xlen_nonconst(struct target *target)
|
||||
static unsigned int riscv_xlen_nonconst(struct target *target)
|
||||
{
|
||||
return riscv_xlen(target);
|
||||
}
|
||||
|
|
@ -5981,7 +5981,7 @@ int riscv_init_registers(struct target *target)
|
|||
} else if (r->exist && !list_empty(&info->hide_csr)) {
|
||||
range_list_t *entry;
|
||||
list_for_each_entry(entry, &info->hide_csr, list)
|
||||
if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
|
||||
if (entry->low <= csr_number && csr_number <= entry->high) {
|
||||
LOG_TARGET_DEBUG(target, "Hiding CSR %d (name=%s)", csr_number, r->name);
|
||||
r->hidden = true;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1948,13 +1948,13 @@ static int target_call_timer_callbacks_check_time(int checktime)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int target_call_timer_callbacks()
|
||||
int target_call_timer_callbacks(void)
|
||||
{
|
||||
return target_call_timer_callbacks_check_time(1);
|
||||
}
|
||||
|
||||
/* invoke periodic callbacks immediately */
|
||||
int target_call_timer_callbacks_now()
|
||||
int target_call_timer_callbacks_now(void)
|
||||
{
|
||||
return target_call_timer_callbacks_check_time(0);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue