Commit Graph

4508 Commits

Author SHA1 Message Date
Xiang W 373b8f1a89 target/riscv: fix execute_fence
This patch improves the following issues:
1. Makes it compatible with targets with progbufsize == 1.
2. Although exceptions don’t update any registers, but  do end execution
of the progbuf. This will make fence rw, rw impossible to execute.

Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6
Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-17 09:05:36 +08:00
Parshintsev Anatoly a8fedebcb4 [riscv] refactor functions that register read/write via progbuf
The motivation for this refactor is to fixup error handling for some
corner cases. These functions attempt to cache S0 register and only then
perform a bunch of extra checks to figure out if the requested register
is valid one in this context. The problem is that there are few corner
cases when _*progbuf functions could receive a GPR as an input. For
example, an abstract read could fail (for whatever reason) leading to
infinite recursion:

````
save S0 -> read S0 -> save S0 -> read S0 -> ...
```

The case described above could be fixed by adding extra sanitity checks,
however I decided to make these functions more modular since I find
self-contained functions easier to read.

Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-15 17:54:00 +03:00
Tim Newsome 9260101307
Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlbl
target/riscv: improve error handling in trigger setup
2023-08-14 09:48:03 -07:00
Kirill Radkin 1d2eea0399 target/riscv: Add support for Sv57 translation mode (including second-stage translations)
Also fix Sv48x4 translation mode
2023-08-14 14:33:44 +03:00
Evgeniy Naydanov 9b558838b1 target/riscv: improve error handling in trigger setup
Change-Id: I235973a3c44fb3d934925c74ffee47f8bd96de0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-08-03 17:58:16 +03:00
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Erhan Kurubas e6f30aef80 src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-20 23:09:06 +02:00
Tim Newsome fb284475a8
Merge pull request #878 from en-sc/en-sc/trigg-eq-check
target/riscv: cleanup trigger setup
2023-07-18 09:32:37 -07:00
Evgeniy Naydanov a8f28fdd48 target/riscv: cleanup trigger setup
* Add a warning when eq trigger is setup and it's behavior is different
from other triggers.

* Make eq trigger's behavior consistent with other triggers in case of
length == 1.

* Fix a bug in setting chained triggers (LT, GT case).

* Improve logging.

Change-Id: Id1ed0d11971b8ed875afbb979e6c8a8b51dd3818
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-17 20:41:01 +03:00
Tim Newsome b67b80c6ac
Merge pull request #879 from riscv/power_dance3
target/breakpoints: Clear software breakpoints from available targets
2023-07-17 09:30:41 -07:00
Tim Newsome 814a3b5e7b
Merge pull request #871 from en-sc/en-sc/fix-mdx-err
target/riscv: refactor read_memory_progbuf()
2023-07-17 09:30:11 -07:00
Evgeniy Naydanov 8d660ea98d target/riscv: refactor read_memory_progbuf()
There were a couple of problems with previous implementation:

* Misalligned read would return ERROR_OK and print all zeroes.

* CMDERR_BUSY for abstract access was improperly handled:

According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.

* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.

Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-14 22:23:02 +03:00
Mark Zhuang d5425c253c target/riscv: dynamic allocate memory for hawindow
Change-Id: Id2f1a2568a39eec0a9dd4fe0f155619b11f9d6ba
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:47 +08:00
Mark Zhuang 04d8cfc48c target/riscv: update some macro
1. update RISCV_MAX_HARTS to 2^20 according to SPEC
2. remove RISCV_MAX_REGISTERS, it's not used anywhere anymore
3. add parentheses

Change-Id: Iadf0fa1ba3bbe5b9420b8430883e140db87f4f9e
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:44 +08:00
Tim Newsome 674911ef18 Merge commit 'a3ed12401b1f7d9578fb7da881d3504e07acfc27' into from_upstream
Conflicts:
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I65bdb4d28c91e9022ce811de976c9bf474a0b590
2023-07-12 16:32:38 -07:00
Tim Newsome 122c54b4c2 target/riscv: Message when harts become available.
Change-Id: I3824e215a845ba7df3c7887ce1693378fde94b4b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:43 -07:00
Tim Newsome 39a4f37f84 target/breakpoints: Clear software breakpoints from available targets
If a target where a software breakpoint was set is not currently
available, but there are other targets in the same SMP group that are
available, then we can use those to remove the software breakpoint.

Change-Id: I9faa427c7b3aee31504e6e6599539e6f29b58d8f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:40 -07:00
Tim Newsome 162cc1e79d target/riscv: Fix typo in gdb_regno_cacheable() comment.
Change-Id: If8806853d47779b5b208202803ed5da437f7b624
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-06 10:40:59 -07:00
Tim Newsome 21d21408aa
Merge pull request #872 from aap-sc/aap-sc/smp_manipulation
[target/riscv] support for smp group manipulation
2023-07-06 09:10:11 -07:00
Marek Vrbka ea115917b9 target/riscv: Fix the trigger writing sequence
According to section 5.6 in the RISC-V debug specification, the previous
way to set triggers was incorrect, as was discussed as part of
https://github.com/riscv/riscv-openocd/issues/870. This commit fixes the
sequence to be in line with the specification as well as adds some comments
to clarify for any future reader as to what is actually done.

Change-Id: Iffc5cc0f866a466a7aaa72a4c53ee95c9080ac9d
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-04 12:04:02 +02:00
Parshintsev Anatoly 2903daa9f1 [target/riscv] support for smp group manipulation
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior

Change-Id: I469453d95e7c1640a91bc60d80c854404e508535
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-07-03 17:28:40 +03:00
Tim Newsome 92c0319261
Merge pull request #873 from eosea/bscan_tunnel_seg_fault_fix
Add null pointer check before right shift for bscan tunneling.
2023-06-29 10:09:12 -07:00
Mark Zhuang 34418ed1c8 target/riscv: fix haltgroup_supported to info->haltgroup_supported
Change-Id: Id1276aecd3097d90e035bf3808e0c472188ba474
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-06-27 15:46:23 +08:00
eolson 9d23d3774a Add null pointer check before right shift for bscan tunneling.
Change-Id: I5d4764c777f33d48705b3e5273eb840c13cfbfb7
Signed-off-by: eolson <erin.olson@seagate.com>
2023-06-22 13:11:15 -05:00
Tim Newsome 470c2a402c
Merge pull request #868 from en-sc/en-sc/upstream-resume-err-2
target/riscv: resume only halted harts
2023-06-21 09:37:40 -07:00
Tim Newsome 1bcabbebb7
Merge pull request #857 from riscv/power_dance2
When dcsr.ebreak* might be cleared, halt the target and set it again
2023-06-21 09:32:23 -07:00
Evgeniy Naydanov 8ca5c2fbe4 target/riscv: resume only halted harts
With this change, failures to resume a hart due to it not being halted
are more explicitly logged or reported as an error.

Change-Id: Ia55d8df85a908363d0f2140637ce1e47c1ab6251
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-06-21 11:44:38 +03:00
Tim Newsome bf07ddef8a target/riscv: From tick(), set ebreak* if necessary.
This involves halting the target, which might have unintended side
effects, but when the debugger is connected software breakpoints must
trap to the debugger. Anything else is a terrible user experience.

Change-Id: I1f7bb610eeeb054cc3042dc6bcfc16589ce12a31
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:59:45 -07:00
Tim Newsome da5bf318b9 target/riscv: Track whether ebreak* is set.
We need to know, so we can set it when necessary.

Change-Id: I1f0d5107f1208f7b9316e15870f0804e51232dee
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:49 -07:00
Tim Newsome 87bfe9f505 target/riscv: Add periodic tick() callback
Intended as a place where we can interact with the target without too
much concern about preserving state and doing exactly the right thing
while poll() is going on.

Change-Id: Ic9bd441caae85901a131fd45e742599803df89b5
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:49 -07:00
Tim Newsome 34f9ff0d0d target/riscv: Add some event callbacks.
Specifically, call into the RISC-V version when target becomes halted,
running, or unavailable.

I'll be using unavailable shortly.

Change-Id: I9ffffdccbf22e053fe6390d656b362bf9ab9559a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:44 -07:00
Tim Newsome 6e64b685f4 target/riscv: Track whether halt groups are supported.
Will be used later when we want to do a quick halt/resume.

Change-Id: Ib80166234c4c277b7d9ce26b7566ac0f93017e64
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:31 -07:00
Tim Newsome b496bebcda target/riscv: Improve update_dcsr()->set_dcsr_ebreak()
* Only set ebreak bits that might be supported based on misa.
* Don't write dcsr if its value wouldn't change.

Change-Id: I7087af0b0df0fbdbf994373b5c887b9b389df872
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 9d8bbb559d target/riscv: Tweak set_group().
Make it callable earlier, handle `supported` being NULL, and make enum
names more clear.

Change-Id: If4d286b54ccfc01eb5de5a57eb18f748c920e979
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 866282ba9e target/riscv: Add debug msg to reset_delays_wait
Makes it easier when reading debug logs.

Change-Id: I3938437357e0d74e1cda680693f907a20c5579c7
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 2a64da39b0 target/riscv: Remove unused riscv013_on_halt function
The riscv013_on_halt function was being called but its implementation was
empty, providing no additional functionality. Removed the function declaration,
calls to it, and its implementation since it is not required.

Change-Id: I425ea890deadeec945f0a47af247f3f99172e801
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome ebfd43c84f target/riscv: Early exit magic sequence checks in riscv_semihosting
When halted we don't need to read all 3 instructions before deciding the
sequence doesn't match.

Change-Id: I9f8345960ce27e859265af901a368166a70b9fde
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-15 10:40:37 -07:00
Marek Vrbka 9f23a1d7c1 semihosting: fix non-zero value on Windows isatty()
On Windows, isatty() can return any non-zero value if it's an interactive
device. Which diverges from the ARM semihosting specification. This patch
introduces a fix to make the SYS_ISTTY operation conform to spec.

Change-Id: I9bc4f3cb82370812825d52419851910b3e3f35cc
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7725
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-06-10 17:10:27 +00:00
Marek Vrbka 0854c83076 gdb_server: add debug signal reason prints
Added debug prints to show what is the target debug reason. Also added
debug print for Ctrl-C response. This is useful for troubleshooting and
log analysis.

Change-Id: I055936257d989efe7255656198a8d73a367fcd15
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7720
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-06-10 17:00:26 +00:00
Tim Newsome 166b68c1b0 target/riscv: Remove unnecessary prototypes.
These functions used to exist but don't anymore. (Pointed out in #863)

Change-Id: Iac6b5edd320bdff7628a788861e332f956dcd93d
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-09 15:13:44 -07:00
Tim Newsome 973c72887c
Merge pull request #860 from riscv/examine_state
target/riscv: set_dcsr_ebreak() while target->state is still changed
2023-06-08 09:10:55 -07:00
Tim Newsome ad89d570e7 target/riscv: set_dcsr_ebreak() while target->state is still changed
Otherwise it fails.

Fixes #859.

Change-Id: Ib59e6d840316b881481a9b1e01f9d546e73bf932
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-07 09:49:58 -07:00
Marek Vrbka 711ac4f0f0 target/riscv: add register cache flushing and invalidation to protobuf execution.
Previously, progbuf execution did not flush or invalidate the register cache which could lead to incorrect behavior. This patch fixes it as well as refactors few sore points in the code related to it.

Change-Id: I353b931ca70a1828d4a9cc512aead00441730875
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-06-07 09:41:30 +02:00
Tim Newsome 0ab2ebd191 target/riscv: Select hart in update_dcsr()
Otherwise we may end up modifying DCSR of a different hart than
intended.

Change-Id: I39bde21a1444623ed150f2b3d504b9318b9d6191
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-05 09:39:14 -07:00
Erhan Kurubas 4dc4280555 target/espressif: fix clang scan-build warning
Clang reports that 3rd function call argument is an uninitialized value
file esp32_apptrace.c line:1270

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I73e254d4eb0c6b3152229717d8827d334784ab92
Reviewed-on: https://review.openocd.org/c/openocd/+/7719
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-06-02 21:00:32 +00:00
Bohdan Tymkiv 72131e05e9 cortex_m: fix reading of DCB_DSCSR register
Value in the 'dscsr' variable is garbage until the DAP queue is run.
Postpone evaluation of the 'secure_state' variable. Reading the
core registers in between will execute the DAP queue.

Change-Id: I44959e882dbafb1b9779e813c3d13f3b3dbcd47f
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7693
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-06-02 20:57:49 +00:00
Antonio Borneo 4a57f3ebb2 target: armv8: fix support of pointer authentication
The registers pauth_dmask and pauth_cmask are not accessible in
AARCH32 mode. Tagging them as 'hidden' is not enough and triggers
error:
	Failed to read pauth_dmask register
while halting the core.

Tag the pauth registers as not existing, unless required by user.

Note: for non existing registers there should be no need to
      allocate their register cache. Let's keep this for a further
      improvement.

Change-Id: Iaa0d006a3d8ee611ee93333ed49a8615a6c94276
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: d0436b0cda ("armv8: Add support of pointer authentication")
Reviewed-on: https://review.openocd.org/c/openocd/+/7712
Tested-by: jenkins
Reviewed-by: Koudai Iwahori <koudai@google.com>
2023-06-02 20:57:05 +00:00
Tim Newsome 5a9654d272
Merge pull request #854 from en-sc/en-sc/fix-regacc-running
target/riscv: fix register access on running target
2023-06-02 08:25:07 -07:00
Evgeniy Naydanov 3a29542056 target/riscv: fix register access on running target
Register access on running target should fail if mstatus needs to be
modified.

Change-Id: Iec8e8d514ef2f5ca42606a5534cce55aaaa99180
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-31 22:22:53 +03:00
Ian Thompson 2dd34cbe0b target/xtensa: add file-IO support
- Manual integration of File-IO support from xt0.2 release
- Verified with applications linked using gdbio LSP
- No new clang static analysis warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: Iedc5f885b2548097ef4f11ae1a675b5944f5fdf0
Reviewed-on: https://review.openocd.org/c/openocd/+/7550
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27 06:43:59 +00:00
Antonio Borneo 8297836170 jtag: rewrite jim_jtag_tap_enabler() as COMMAND_HANDLER
The function is used for commands:
- jtag tapisenabled
- jtag tapenable
- jtag tapdisable

While there, add the missing .help and .usage fields and fix the
incorrect check in jtag_tap_enable() and jtag_tap_disable().

Change-Id: I0e1c9f0b8d9fbad19d09610a97498bec8003c27e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7554
Tested-by: jenkins
2023-05-27 06:42:51 +00:00
Antonio Borneo 5dd047fbbe jtag: rewrite commands 'jtag newtap' and 'swd newdap' as COMMAND_HANDLER
While there:
- fix memory leak in case of error on values tap->chip,
  tap->tapname, tap->expected_ids;
- check for out of memory error;
- fix minor coding style issue;
- add the missing .usage field;
- remove functions not in use anymore.

Change-Id: I1c8c3ffeb324e9eacb919c7e0d94fd72122c9a81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7431
Tested-by: jenkins
2023-05-27 06:42:01 +00:00
Antonio Borneo da76f8f0b4 target: use unsigned int for timeout_ms
Change the prototype of functions:
- target_run_algorithm()
- target_wait_algorithm()
- target_wait_state()
- struct target_type::run_algorithm()
- struct target_type::wait_algorithm()
to use unsigned int for timeout_ms instead of int.
Change accordingly the variables passed as parameter.

Change-Id: I0b8d6e691bb3c749eeb2911dc5a86c38cc0cb65d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7562
Tested-by: jenkins
2023-05-27 06:41:17 +00:00
Antonio Borneo fe6befbd80 target: rewrite command 'arp_waitstate' as COMMAND_HANDLER
While there, add the missing .usage field and remove the now
unused function jim_target_tap_disabled().

Change-Id: I79afcc5097643fc264354c6c3957786a55f40498
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7561
Tested-by: jenkins
2023-05-27 06:40:40 +00:00
Antonio Borneo 22ababc12e target: rewrite command 'arp_examine' as COMMAND_HANDLER
Change-Id: I8f227b219ca39f198e1e39847ddd36bb9880a328
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7560
Tested-by: jenkins
2023-05-27 06:40:16 +00:00
Antonio Borneo 0f0a4b1452 target: espressif: apptrace: declare a local function as static
The function esp32_cmd_apptrace_generic() is not used outside the
file.

Declare it as static.
Detected through 'sparse' tool.

Change-Id: I08c6b92fb01594320bc3ae6b16067ac4eb51ca12
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7676
Tested-by: jenkins
2023-05-27 06:39:35 +00:00
Erhan Kurubas a0fecd6c41 target/espressif: add system level tracing feature
Produces traces compatible with SEGGER SystemView tool.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: If1057309edbb91ed2cf1ebf9137c378d3deb9b88
Reviewed-on: https://review.openocd.org/c/openocd/+/7606
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27 06:38:51 +00:00
Antonio Borneo 144d940a8b Revert "target/image: zero-initialize ELF segments up to p_memsz"
This reverts commit 047b1a8fc2.

Commit 047b1a8fc2 ("target/image: zero-initialize ELF segments
up to p_memsz") breaks the backward compatibility introducing some
problem:
- an empty bss segment with paddr in SRAM gets zero filled at load
  but does not survive after a reset, causing verify to fail;
- an empty bss segment with paddr in FLASH causes excessive flash
  usage, which can exceed flash size (causing error) and makes
  flash aging faster.

Revert it while looking for a better implementation.

Change-Id: Iaaf926dafce46a220a5bbe20c8576eb449996d76
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7658
Reviewed-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Peter Collingbourne <pcc@google.com>
Tested-by: jenkins
2023-05-27 06:38:12 +00:00
Tim Newsome f0898155d1 target/riscv: Set dcsr.ebreak* during examine()
This way if you connect to a running target, before it's hit a breakpoint,
then when it does hit the breakpoint OpenOCD will catch it.

Change-Id: I6f1e5f169fa385f46759015786e664693c3872e4
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:01:47 -07:00
Tim Newsome 21433e83ee target: poll() failure does not mean the target halted.
Poll failure just means poll failed. It's safer to assume the target is
still running, because then if it is running and subsequently halts we can
relay this to gdb correctly. We can't do the other way around, because once
gdb thinks the target has halted, it can't deal with it spontaneously
running.

Change-Id: Idb56137f1d6baa9afc1b0e55e4a48f407b8ebe83
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 82ed02f92a target/riscv: Always clear progbuf cache in examine().
When a DM was powered down, we end up in examine() again, and clearly if
the DM was powered down we need to invalidate that cache.

Change-Id: I5eb6a289939f313e06c09cac22245db083026aa3
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 1c5cf8023c target/riscv: Reset DTM when it reports an error.
The error state is sticky, so this has to be done to recover.

Change-Id: I589f3cdab0f2351fd25f89951830cbc16c39bd93
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Amaury Pouly 5924d9f30c target/riscv-013: clear sticky error when DMI operation fails
When a DMI operation does not succeed (either because of a timeout
or an error), the specification says that the error in the `op`
field is sticky and needs to cleared by writing `dmireset` in `dtmcs`.
This is already done for timeouts in increase_dmi_busy_delay
but not for errors.

Change-Id: I7c5f27a5cf145511a1a8b64a45a586521e1cbe41
Signed-off-by: Amaury Pouly <amaury.pouly@lowrisc.org>
Reviewed-on: https://review.openocd.org/c/openocd/+/7688
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-25 16:19:12 +00:00
Evgeniy Naydanov 5a29a7399f target/riscv: refactor register accesses
Change-Id: I45731d501f6261c4142c70afacf3fbbe42cf2806
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-23 20:20:19 +03:00
Evgeniy Naydanov c822dc8194 target/riscv: improve register caching (prep_*, cleanup_*)
Introduce riscv_write_register to prep_for_register/vector_access and
cleanup_after_register/vector_access.

Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 8f3a617dc7 target/riscv: improve register caching (riscv_write_register)
This commit introduces a new function, which can be used to reduce number
of register accesses.

Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 7a181e8bbc target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently
Change-Id: Ia476251e835fa5fd129ae6b679c6049c5c60c716
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 919a98a05b target/riscv: fix register cache flushing
Since writing a register can make some GPRs dirty (e.g. S0, S1), registers
should be flushed in reverse order, so GPRs are flushed last.

Change-Id: Ice352a4df4ae064619c0f9905db634a7b57e4711
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Tim Newsome 461eb65e21
Merge pull request #847 from riscv/data1_cache
target/riscv: Comment that data1 might change.
2023-05-18 10:56:00 -07:00
Antonio Borneo fb34eeb442 target: arm_adi_v5: move in include file the declaration of dap_ops
The struct containing SWD and JTAG operations are declared as
extern in the C file.

Mode them in include file arm_adi_v5.h to silent 'sparse' error
for global variable definition without declaration in an include
file.

Change-Id: I59088512c052d5a120c38404a882ed512a68ca02
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7675
Tested-by: jenkins
2023-05-18 10:16:12 +00:00
Antonio Borneo d5c177cd3d server: gdb: export gdb_actual_connections through a function
The internal variable 'gdb_actual_connections' is used by log and
by semihosting to determine if there are active GDB connections.

Keep the variable local in server's code and only export its value
through a dedicated function.

This solves the issue detected by 'parse' of the variable defined
as global but not declared in any include file.

Change-Id: I6e14f4cb1097787404094636f8a2a291340222dd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7673
Tested-by: jenkins
2023-05-18 10:14:56 +00:00
Antonio Borneo d15f58ad4c target: arm_dpm: with pointers, use NULL instead of 0
Don't assign pointer to 0, use NULL.

Detected through 'sparse' tool.

Change-Id: I34551112ddab9dedf8537c8111d32356c170e7d5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7669
Tested-by: jenkins
2023-05-18 10:11:53 +00:00
Antonio Borneo ed46188a72 target: move in target_type.h the target_type's declaration
The static analyser 'sparse' complains, while compiling a target's
file, that the struct target_type is declared in the file as non
static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of target_type's declaration in target_type.h
While there, fix a name clash in stm8.c

Change-Id: Ia9c681e0825cfd04d509616dbc04a0cf4944f379
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7659
Tested-by: jenkins
2023-05-18 09:54:59 +00:00
Tim Newsome be5187d0a8 target/riscv: Comment that data1 might change.
In case in the future I have the same idea of optimizing progbuf writes
again.

Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-17 09:46:23 -07:00
Tim Newsome d78d991191
Merge pull request #850 from riscv/cleanup-in-target-c
Minor cleanup in target.c
2023-05-16 09:27:57 -07:00
Tim Newsome 15bd33cc20
Merge pull request #844 from riscv/from_upstream
Merge 228fe7 from upstream
2023-05-15 08:17:31 -07:00
Jan Matyas bd275ef483 Minor cleanup in target.c
Small cleanup in target.c to get rid of few upstream differences:

- removed a pointless check for `reg->exists` - already checked
  few lines above
- unify one log message with what's in upstream

Change-Id: I3fd761157382670611fa90de84e2dfc90192f473
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-15 15:09:55 +02:00
Antonio Borneo 85b5c51806 target: rewrite command 'arp_reset' as COMMAND_HANDLER
While there, add the missing .usage field and move in target.c the
enum nvp_assert.

Change-Id: Ia4f2f962887b5a35faeaa4eae128fa2865569b24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7559
Tested-by: jenkins
2023-05-13 08:55:55 +00:00
Antonio Borneo b931286ab4 target: rewrite command 'arp_halt' as COMMAND_HANDLER
While there, add the missing .usage field.

Change-Id: I748382cafe08443c458ff1d4e47819610cfbf85c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7558
Tested-by: jenkins
2023-05-13 08:55:14 +00:00
Antonio Borneo 219412f9d6 target: rewrite command 'arp_poll' as COMMAND_HANDLER
While there, add the missing .usage field.

Change-Id: I16e0aeacdaaada09fa77ad29552fa4025eff0c45
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7557
Tested-by: jenkins
2023-05-13 08:54:37 +00:00
Antonio Borneo 599f1cf763 openocd: trivial replace of jim-nvp with new nvp
For some trivial case only, replace calls to jim-nvp with calls
to the new OpenOCD nvp.

Change-Id: Ifd9aff32b67748af8ab808e6a6b6e64f5271b888
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7553
Tested-by: jenkins
2023-05-13 08:49:05 +00:00
Antonio Borneo 160288137a xtensa: fix build with gcc 13.1.1
New gcc does not understand that the variable 'restore_ms' is set
to 'true' only when the variable 'ms' is assigned in
	static int xtensa_write_dirty_registers(...)
	{
		xtensa_reg_val_t ms;
		bool restore_ms = false;
		...
		if (...) {
			ms = regval;
			restore_ms = true;
			...
		}
		...
		if (restore_ms) {
			USE(ms);
		}
		...
	}
and complains about possible use of uninitialized variable 'ms'.

Sadly initialize 'ms' to zero to hide this false positive.

Change-Id: I1fb3949070c8abbf4aa45a740f0ca2fdb753d4fa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7681
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
2023-05-13 08:47:27 +00:00
Tim Newsome 57d20e4d96 target/riscv: Remove non-functional code in riscv_program_exec().
Addresses #845.

Change-Id: If4eee383f92946669a84f92e52a3ac3600707525
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-10 16:58:09 -07:00
Antonio Borneo 329b10754a target: etm: fix check trace status
Current code tests a function pointer against a numeric value that
is the same enum type as returned by the pointed function.
Clearly the author was willing to call the function and check its
returned value.

Fix the check by calling the function.

Detected through 'sparse' tool.

Change-Id: I27d18d26c2c797160a397daa32835c199014b70b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Checkpatch-ignore: GIT_COMMIT_ID
Fixes: 237e894805 ("reworked etm/etb into a generic etm part with trace capture")
Reviewed-on: https://review.openocd.org/c/openocd/+/7599
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-05-06 13:34:32 +00:00
Antonio Borneo d771d7f1a7 target: with pointers, use NULL instead of 0
Don't assign pointer to 0, use NULL.
Don't pass 0 ad pointer argument, pass NULL.

Detected through 'sparse' tool.

Change-Id: I806031d2ae505fa5f0accc6be1936d48cd365ca4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7604
Tested-by: jenkins
2023-05-05 22:14:29 +00:00
Antonio Borneo 4b7dc55738 target: rtt: include rtt.h
Let source file to include its file .h to validate the exported
prototypes.

Detected through 'sparse' tool.

Change-Id: I8ae2f8f1fdaea5683e157247463533b17237e464
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7602
Tested-by: jenkins
2023-05-05 22:14:11 +00:00
Antonio Borneo ea62f8e22a target: use 'ULL' suffix for long constants
On 32 bit hosts, gcc should consider constants without suffix as
32 bits values.

Use the suffix 'ULL' to guarantee it is a 64 bit.

Detected through 'sparse' tool.

Change-Id: I205ca986968fef9a536f87492d1f6c80e41829f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7601
Tested-by: jenkins
2023-05-05 22:10:18 +00:00
Tim Newsome da44fb5407 Merge commit '228fe7300c7df7aa05ba2c0bc19edde6d0156401' into from_upstream
Conflicts:
	doc/openocd.texi
	src/jtag/aice/aice_pipe.c
	src/jtag/aice/aice_usb.c
	src/rtos/FreeRTOS.c
	src/rtos/hwthread.c
	src/rtos/rtos_standard_stackings.c
	src/target/riscv/riscv.c

Change-Id: I0c6228c499d60274325be895fbcd8007ed1699bc
2023-05-04 14:38:10 -07:00
Tim Newsome 80d529cad3
Merge pull request #843 from riscv/hypervisor_translate
target/riscv: Support hypervisor address translation
2023-05-04 09:52:54 -07:00
Antonio Borneo 8670ad4caa target/espressif: fix clang report on list use
It looks like a false positive.
Scan-build considers as possible to:
- have list_empty() return false;
- list_for_each_safe() to not execute any loop, thus not assigning
  a non-NULL value to 'block';
- the NULL pointer 'block' is passed to list_del().
This is not possible because with list_empty(), the loop runs at
least once.

Rewrite the function to simplify the code and making it easier for
scan-build to check it.

This also drops an incorrect use of list_for_each_safe(), where
the 'safe' version was not required.

Change-Id: Ia8b1d221cf9df73db1196e3f51986023dcaf78eb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8d1dcf293a ("target/espressif: add application tracing functionality over JTAG")
Reviewed-on: https://review.openocd.org/c/openocd/+/7608
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
2023-04-30 14:52:36 +00:00
Antonio Borneo c1dc7935f7 target/espressif: fix clang report on use of garbage value
When the function xtensa_queue_dbg_reg_read() returns error, the
array 'tmp' remains not initialized and scan-build complains while
computing buf_get_u32() that:
	Result of operation is garbage or undefined

Check the returned value of xtensa_queue_dbg_reg_read() and
propagate it.

Change-Id: If0aaad068b97ef0a76560e262d16429afd469585
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8d1dcf293a ("target/espressif: add application tracing functionality over JTAG")
Reviewed-on: https://review.openocd.org/c/openocd/+/7607
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-04-30 14:52:18 +00:00
Erhan Kurubas bb073f897c src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-04-30 14:51:42 +00:00
Julien Massot 2096afc1b0 aarch64: Add support for ARMv8-R
ARMv8-R platforms are similar to ARMv8-A regarding
JTAG and most cpu registers. ARMv8-R doesn't has MMU
but has MPU instead.

ARMv8-R platforms can be AArch32 only such as Cortex-R52,
or AArch64 capable like Cortex-R82.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ib086f71685d1e3704b396d478ae9399dd8a391e1
Reviewed-on: https://review.openocd.org/c/openocd/+/6843
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30 14:46:25 +00:00