Commit Graph

4508 Commits

Author SHA1 Message Date
Tim Newsome 2676f05f2f
Merge pull request #947 from riscv/from_upstream
From upstream
2023-11-03 10:13:05 -07:00
Tim Newsome 20bcd83bca
Merge pull request #945 from kr-sc/kr-sc/fix-mmu-access-upstream
target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
2023-11-02 09:33:55 -07:00
Tim Newsome e474d1d54a target/riscv: Prevent dump_field() reading uninitialized memory
Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-30 09:21:19 -07:00
Kirill Radkin 57c3f0d91c target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
Now:
1) If mmu is disabled, virt2phys succeeded and returns physical address
2) If mmu is enbaled, but translation fails, read/write_memory fails

Change-Id: I312309c660239014b3278cb77cadc5618de8e4de
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-30 15:59:41 +03:00
Tim Newsome f02fe0960c Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstream
Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-27 09:00:59 -07:00
Tim Newsome 89260a5f1f
Merge pull request #942 from riscv/from_upstream
From upstream
2023-10-27 08:46:43 -07:00
Evgeniy Naydanov 57b67eda38 target/riscv: update debug register printers
Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-10-25 19:16:36 +03:00
Tim Newsome 2d98ef5d13
Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstream
hgatp_mode in riscv_virt2phys_v defined by vsatp value
2023-10-24 07:57:37 -07:00
Tim Newsome af08d582b5 Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstream
Conflicts:
	src/flash/nor/drivers.c
	src/target/riscv/riscv.c

Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-23 12:29:21 -07:00
Tim Newsome 132e3faf1d
Merge pull request #940 from riscv/revert-908-disable-soft-bp-size-2-non-compressed
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"
2023-10-23 11:45:50 -07:00
Kirill Radkin 109772012a hgatp_mode in riscv_virt2phys_v defined by vsatp value
Replace `vsatp` with `hgatp` (how it should be)

Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
2023-10-23 18:56:40 +03:00
Tim Newsome 3b0561d081
Merge pull request #935 from riscv/from_upstream
Merge down up to 0384fe5 from upstream.
2023-10-23 08:38:48 -07:00
Tim Newsome 912de786a4
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported" 2023-10-20 15:37:28 -07:00
Tim Newsome a495dd854c
Merge pull request #934 from kr-sc/kr-sc/revert-commit
Revert "target: Update messages connected with `examine`"
2023-10-17 09:46:31 -07:00
Kirill Radkin 6c96b9d8c3 Revert "target: Update messages connected with `examine`"
This reverts commit a3db93b1ce.

Reason for revert: https://github.com/riscv/riscv-openocd/pull/931#issuecomment-1761550506
2023-10-17 12:57:39 +03:00
Tim Newsome 53fcf14d83 Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstream
Conflicts:
      .github/workflows/snapshot.yml
      src/rtos/FreeRTOS.c

Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-16 12:30:06 -07:00
Tim Newsome e1fa78d1b3
Merge pull request #929 from aap-sc/riscv
do not assume DTM version unless dtmcontrol is read successfully
2023-10-16 12:10:25 -07:00
Tim Newsome beb705912b
Merge pull request #917 from kr-sc/kr-sc/disable-triggers-option
provide riscv-specific controls to disable triggers from being used for watchpoints
2023-10-11 12:34:07 -07:00
Tim Newsome 41d1ee3715
Merge pull request #931 from kr-sc/kr-sc/update-examine-messages
target: Update messages connected with `examine`
2023-10-11 12:33:38 -07:00
liangzhen 3f1339f8e8 target/riscv: use cacheable read/write function to handle DCSR
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-07 09:26:31 +08:00
Parshintsev Anatoly 2c4118ecea do not assume DTM version unless dtmcontrol is read successfully
Change-Id: I5f2003b7ac5ce87af6ca9a4fcb46140682a8cfdf
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-10-06 18:51:53 +03:00
Tim Newsome 599e0a22e8
Merge pull request #915 from riscv/dpc_print
target/riscv: Remove duplicate read PC message
2023-10-05 12:05:16 -07:00
Kirill Radkin a3db93b1ce target: Update messages connected with `examine`
Move `examine_attempted` flag to target struct to make it target specific.
`Info` messages for retry and `Error` messages for failure added.

Change-Id: Id2fbe7dc68d746c936c8412289d0d149fbd80d71
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-03 16:28:28 +03:00
Kirill Radkin e76a9b799d provide riscv-specific controls to disable triggers from beeing used for watchpoints
Add a new riscv specific commands to disable triggers

Change-Id: Ic1842085aa66851c740e0abcbfbe0adbe930920e
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-02 11:54:07 +03:00
Tim Newsome 2f1714789b
Merge pull request #921 from lz-bro/repeat_read-fix
target/riscv: support riscv repeat_read by sysbus access
2023-09-29 09:31:59 -07:00
Tim Newsome 75b5de67df
Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreak
openocd does not allow to query status of dcsr.ebreak{u,s,m}
2023-09-29 09:30:46 -07:00
Tim Newsome ef3be96ba1
Merge pull request #892 from en-sc/en-sc/register-printing
target/riscv: define register printers
2023-09-28 08:36:36 -07:00
Kirill Radkin ee2bc807eb openocd does not allow to query status of dcsr.ebreak{u,s,m}
Extend riscv set_ebreak* commands.
Now it can be called without args to print current value.

riscv_ebreak* flags are moved to riscv_info struct.

Change-Id: Ib46e6b6dfc0117599c7f6715c7aaf113e63bd7dc
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-26 11:52:30 +03:00
Tim Newsome 3acc277e49 target/riscv: Remove duplicate `read PC` message
Change-Id: Ie085758e3cf193f2671ea53fb82fd401d0c52d86
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-25 11:41:04 -07:00
Tim Newsome b5e57e1894
Merge pull request #913 from riscv/from_upstream
From upstream
2023-09-25 09:21:09 -07:00
Evgeniy Naydanov 43ebdd47a5 target/riscv: define register printers
`riscv_debug_reg_to_s()` can be used to decode register value.  If the
pointer to buffer is `NULL` it does not print anything, just returns the
length of the string.

The format is:
`<register_value> { <field_name>=<field_value_name or field_value>, ..., }`

e.g:

`0x400382 { version=2, ... ndmresetpending=false, }`

`0x321009 { regno=0x1009, ... cmdtype=0, }`

Change-Id: I63733d8d36385d89ca15de1a43139134bc488c4f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-22 16:26:28 +03:00
liangzhen a8ffda6e70 target/riscv: support riscv repeat_read by sysbus access
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-09-21 15:33:17 +08:00
Tim Newsome 2c2135a0cb target/riscv: Don't assert in riscv013_get_register()
When the target isn't halted, simply return an error. This used to be
purely internal code so an assert was appropriate. Now after some
refactoring and with unavailable harts you could get here when the hart
is unavailable. In that case the right thing is simply to return an
error message.

Change-Id: I49d26a11fe7565c645fd2480e89a2c35ea9b1688
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-13 13:44:20 -07:00
Tim Newsome fb26f4f89d target/xtensa: Fix build warning.
Change-Id: I9ee69807bec729480dd94da874fe1771d8f06078
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-12 13:11:05 -07:00
Tim Newsome 8c1f1b77d3 Merge commit 'ee31f1578a333a75737bc5b183cd4ae98cdaf798' into from_upstream
Conflicts:
	Makefile.am
	jimtcl
	src/helper/Makefile.am
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/rtos/rtos_standard_stackings.c

Change-Id: I00c98d20089558744988184370a8cb7f95f03329
2023-09-12 12:55:10 -07:00
Tim Newsome 67c2835997
Merge pull request #911 from riscv/from_upstream
From upstream
2023-09-11 12:53:42 -07:00
Tim Newsome 53f21336c4
Merge pull request #912 from MarekVCodasip/make-unknown-semihosting-error
target/riscv_semihosting: Make the unknown operation number an error
2023-09-08 09:22:10 -07:00
Tim Newsome 42dcc99026
Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggers
target/riscv: cleanup riscv_enumerate_triggers()
2023-09-08 09:21:55 -07:00
Evgeniy Naydanov c286f938f4 target/riscv: cleanup riscv_enumerate_triggers()
1. Propagate error codes.
2. Disable leftover triggers in case `tinfo` is supported.

Change-Id: Ie20edb4d8b9245e13ac8757bf6afe549ac99c4f1
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-07 13:39:50 +03:00
Marek Vrbka 1936dbd6cf target/riscv_semihosting: Make the unknown operation number an error
Previously, an unknown semihosting operation number
was logged as debug. This patch changes it and few
other places to be logged as error instead.

Change-Id: I83cae5ca1e3daed440f92b08bd372bfffbbad63c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-07 08:08:06 +02:00
Marek Vrbka 8ad41767c0 target/riscv: Reject size 2 soft breakpoints when C extension not supported
This patch disables software breakpoints of size 2 for targets
which don't support compressed instructions.

Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04 07:47:03 +02:00
Tim Newsome 699eecaab4
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
2023-08-30 10:59:54 -07:00
Tim Newsome 0801c66ff4 Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstream
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
2023-08-29 13:10:44 -07:00
Tim Newsome 5efea16944
Merge pull request #900 from aap-sc/aap-sc/simplify_state_managment
riscv: simplify state management during examine
2023-08-29 10:11:52 -07:00
Marek Vrbka 0b914fe5ae target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-25 07:54:59 +02:00
Tim Newsome 928f2b374a
Merge pull request #904 from kr-sc/kr-sc/support-sv57
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23 12:03:21 -07:00
Tim Newsome 7aedb15951
Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_running
fix crash when we try to read vector register on a running target
2023-08-23 12:01:49 -07:00
Tim Newsome 5cb60e3f7d
Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
2023-08-18 09:32:51 -07:00
Parshintsev Anatoly 198edca6d0 riscv: simplify state management during examine
This also fixes a bug when, after `examine` completion, the target still
has  `unknown` status. To reproduce this one spike, it is enough to do
the following:

---
// make sure spike harts are halted
openocd ... -c init -c 'echo "[targets]"'
---

this behavior is quite dangerous and leads to segfaults in some cases

Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 15:29:19 +03:00
Parshintsev Anatoly 0ae47ae472 fix crash when we try to read vector register on a running target
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 00:18:10 +03:00