Commit Graph

4324 Commits

Author SHA1 Message Date
Tim Newsome 88a629c017
riscv/target: Replace is_halted() with get_hart_state() (#756)
Prep work for handling unavailable harts.

Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:04 -08:00
Xiang W 61f183fb25
Use match field for trigger (#725)
* Use match field for trigger

The watchpoint cannot capture all data modifications only through the
trigger of ANY SIZE and EQUAL, and an error will occur. This patch
accommodates watchpoints by adding more types of matches

Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a
Signed-off-by: Xiang W <wxjstz@126.com>

* Add variable type trigger support

Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1
Signed-off-by: Xiang W <wxjstz@126.com>

* remove trailing whitespace

Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84
Signed-off-by: Xiang W <wxjstz@126.com>

* update triggers enumerate

Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f
Signed-off-by: Xiang W <wxjstz@126.com>

Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:48:31 -08:00
Tim Newsome ae3ad22311
target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()

Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>

* Comment code more clearly.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove extra tab

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:39:19 -08:00
Dolu1990 70980e7f57
Fix dm->current_hartid corruption on hartsellen discovery (#754)
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery

Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

* target/riscv Ensure HART_INDEX_DIRTY does not have side effects

Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-11-01 09:51:33 -07:00
Tim Newsome fad123a16b
target: Add TARGET_UNAVAILABLE state. (#752)
This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).

Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-27 15:21:31 -07:00
Erhan Kurubas 535de48ca6 target/xtensa: remove redundant call for `TARGET_EVENT_HALTED`
`xtensa_do_step` is invoked from `xtensa_prepare_resume` to silently
step over BP/WP before resuming.
For example; in the case of WPs (DEBUGCAUSE_DB), in the current
implementation `xtensa_do_step` will generate one more
`TARGET_EVENT_HALTED` after the original one caused by WP itself.

This patch moves the halted event cb call after
the step is done successfully.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9048e14fb316dc124847a42cfaefb1f76b5ce53e
Reviewed-on: https://review.openocd.org/c/openocd/+/7274
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-21 18:16:23 +00:00
Antonio Borneo b8735bbf7e doc: fix riscv commands
- Fix the declaration of riscv command 'set_mem_access'.
- Remove non existing riscv command 'set_scratch_ram'.
- Add riscv commands 'info', 'reset_delays'; copy the description
  from the 'help' text.
- Don't add riscv commands 'set_prefer_sba' and 'test_sba_config_reg'
  as they are marked as deprecated.
- Ensure that 'test_sba_config_reg' prints a deprecation warning
  when used.

Change-Id: I39dc3aec4e7f13b69ac19685f1b593790acdde83
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7268
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
2022-10-21 18:14:46 +00:00
Tim Newsome 9eb07f258e
target/riscv: Correctly set target->state in deassert_reset (#750)
* target/riscv: Correctly set target->state in deassert_reset

This bug didn't lead to problems, but it would with some upcoming
changes.

Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb
Signed-off-by: Tim Newsome <tim@sifive.com>

* Keep debug_reason in sync with state

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-21 09:16:54 -07:00
Erhan Kurubas 3b8333bd3f target/xtensa: fill register number field in the cache
Currently 'number' field is zero in the register cache and
this causes an issue on `rtos get_thread_reg_list` calls.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iaef11e01f55d012969bbc1933f82847d5e02fec5
Reviewed-on: https://review.openocd.org/c/openocd/+/7246
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-15 15:58:44 +00:00
Erhan Kurubas 2d5d8a5a62 target/esp32s2: check xtensa_poll return value
Although scan build couldn't catch, return value overwritten
without checking.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I02b10002b03640604315047e8a8a639824724c16
Reviewed-on: https://review.openocd.org/c/openocd/+/7247
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-15 15:57:57 +00:00
Anatoly Parshintsev fe5c7d7a35
[riscv] step operation handler should respect handle_breakpoints parameter (#741)
* [riscv] step operation handler should respect handle_breakpoints parameter

When step operation is requested the OpenOCD frontend (like gdb server
or TCL server) has an option to control how existing breakpoints are
handled upon step.

Some OpenOCD frontends (like gdbserver) may choose to disable special
handling of existing breakpoints - thus handle_breakpoints is set to 0,
while others (like TCL server) expect target handler to temporary
disable the matching breakpoint to allow the step operation to complete
successfully.

In the current implementation handle_breakpoints parameter was ignored
by target-specific handler. Thus, the following sequence of commands:

```
halt
bp <current_pc> 4
step
```

Resulted in *step* operation to not change PC because of bp match.

This commit addresses this issue.

* Adjusted calls to logging facilities (addressed review comments)

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-14 09:40:16 -07:00
Tim Newsome a50b280558
Properly track selecting multiple harts at once. (#743)
* Properly track selecting multiple harts at once.

use_hasel is a bit of a hack.

Change-Id: Ia589ebc16bca32038d915df9988361b88e940917
Signed-off-by: Tim Newsome <tim@sifive.com>

* Clarifying comment.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Rename set_hartsel to set_dmcontrol_hartsel

Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850

* Make set_dmcontrol_hartsel() more idiomatic.

Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486

* Use constant for multiple harts instead of -1.

Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-12 08:57:00 -07:00
Tim Newsome 4270857a76 target/riscv: Clean up halt_go for multiple harts.
Also add an early exit for if any harts are unavailable.

Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-11 13:57:55 -07:00
Tomas Vanek dc6cad855d target: re-examine before arp_waitstate in ocd_process_reset_inner
arp_waitstate will not work on not-examined state

Change-Id: I56c3e1c7e63af108e4ed1dbacebb567f9bf46264
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7230
Tested-by: jenkins
Reviewed-by: Erwan Gouriou
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:53:51 +00:00
Tomas Vanek 1f84f34850 target/hla_target: try to re-examine under reset in hl_assert_reset()
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.

Try to examine the target under reset as the last resort.

Change-Id: I7c3de39fb1e6c23b76e2a0a85ab75f23aac94c4d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7229
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:52:45 +00:00
Tomas Vanek f65d1da013 target/cortex_m: try to re-examine under reset in cortex_m_assert_reset()
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.

Try to examine the target under reset as the last resort.

Change-Id: Ife875a966a838c37dde987bc584ad0a1f4d020d6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:49:52 +00:00
Tomas Vanek b991c416b7 target/cortex_m: make reset robust again
After merging [1] 'reset halt' does not work on not responding Cortex-M.

Relax the examined tests and try to set vector catch VC_CORERESET
if debug_ap is available.

While on it add an info about examination state to debug logs.

Fixes: [1] commit 98d9f1168c ("target: reset target examined flag if target::examine() fails")
Change-Id: Ie2e018610026180af5997d70231061a275f05c76
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6745
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:46:12 +00:00
Daniel Goehring a69b382efd target/adiv5: 64-bit TAR setup bugfix
For 64-bit TAR setup, if 'tar_valid == false' perform the upper 32-bit
write even if the cached copy matches the upper TAR value to be written.

Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: I320377dc90a9d1d7b64cbb281b2527e56c7621ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7245
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-10-08 07:55:35 +00:00
Erhan Kurubas cff2cf373f target/xtensa: pass correct buffer on read memory retry
Read values must be at albuff so that can be copied to buffer
on function exit.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I74a533e8f12f1002ca06a98a7c7cd928552b4cc5
Reviewed-on: https://review.openocd.org/c/openocd/+/7226
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 07:53:12 +00:00
Erhan Kurubas 10b08d5ac5 target/xtensa: rename pc and ps macro names
Actually they are the base of epc and eps

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I4f43b9609a9929399fb5d3fa0203efc8a98e94c9
Reviewed-on: https://review.openocd.org/c/openocd/+/7227
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 07:52:49 +00:00
Tomas Vanek 48507e3b10 target/armv7m: show target name in 'halted' message
Change-Id: I13e9a33677632d52122585203252fc4ef0c52a2a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7237
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 07:47:09 +00:00
Tomas Vanek bced97cce9 target/armv7m: prevent storing invalid register
armv7m_start_algorithm() stored all non-debug execution
registers from register cache without checking validity.

Check if the register cache is valid.
Try to read from CPU if not valid.
Issue a warning if register read fails.

Change-Id: I365f86d65243230cf521b13909575e5986a87a50
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7240
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-10-08 07:46:16 +00:00
Dmitry Ryzhov 01ae0f2122 Fix incorrect braces caused by #732 2022-10-07 16:34:59 +03:00
Tim Newsome 0f12a01007 riscv: Minor formatting cleanup.
Change-Id: I0256fd047d8369ca7b327172225a9d1f827673c5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-05 10:23:45 -07:00
Tim Newsome 84365e65e5 Remove riscv_info_t.current_hartid
This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).

This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.

Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-30 10:21:38 -07:00
Tim Newsome 550a66e720
Use LOG_TARGET_FOO() functions in more places. (#731)
Change-Id: Id2266dbfb6209bf0676f28e7383a12705ce2a70e
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-29 15:09:49 -07:00
Tim Newsome 23df83e830
Merge pull request #727 from riscv/poll_backoff
Make poll backoff time based.
2022-09-27 10:13:12 -07:00
Tim Newsome e53fd14f50
Merge pull request #733 from en-sc/en-sc/remove-erroneous-debuglog
Remove incorrect debug_log in wait_for_idle
2022-09-27 10:00:40 -07:00
Tomas Vanek 5f14140953 target/adi_v5_swd: suppress reconnect in swd_multidrop_select()
swd_multidrop_select() uses its own retry loop.
If select fails, do_reconnect flag remains set on exit and causes
useless reconnect.

Clear do_reconnect flag in retry loop.

Change-Id: Ie06d6967d7f4a977774c8530bb8d4b3e5ab4f62c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7217
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
2022-09-27 08:29:00 +00:00
Tomas Vanek b2f6b23117 target/adi_v5_swd: fix SWD multidrop
Implementation of ADI v6 introduced banking of DP reg 0.
The accompanying change preventing DP SELECT write before
DP IDR read during connect was added to swd_connect_single() only.
Unchanged swd_connect_multidrop() / swd_multidrop_select_inner()
was broken as it emited DP SELECT and put DP to protocol error state.

Copy dap->select handling to swd_multidrop_select_inner().

Fixes: 72fb88613f (adiv6: add low level swd transport)

Change-Id: I514cd6d9ae2ba97ce3657b459df22638c278a0b1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7213
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-09-27 08:28:44 +00:00
Evgeniy Naydanov fb7c8b310a Remove incorrect debug_log in wait_for_idle
According to RISC-V External Debug Support Version 0.13.2 (paragraph
3.12.6), cmderr field contains a valid value only if busy is 0, so it is
incorrect to analize it on timeout.
2022-09-26 13:52:53 +03:00
Evgeniy Naydanov 137141249b Propagate error code in register_read/write_direct
In some cases error code returned by riscv_program_insert was ignored
2022-09-26 13:37:45 +03:00
Daniel Goehring 1293ddd657 target/target: read_memory 64-bit bugfix
Increase "value_buf" size so it can hold a 64-bit number represented
as a string. Previous size could only hold a 32-bit number string.

Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: If6fbc875236e6ddc59522fbc25db0129eb60ee27
Reviewed-on: https://review.openocd.org/c/openocd/+/7221
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-23 21:26:44 +00:00
Ian Thompson 53d17e7901 target/xtensa: fix final clang analyzer warning
Reworked xtensa_read_memory() logic to always allocate
and initialize working buffer with sufficient padding.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: Ia9ab53336537adebf99f8156f481ca8279a7cd5d
Reviewed-on: https://review.openocd.org/c/openocd/+/7211
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-09-23 21:25:34 +00:00
Antonio Borneo 44ed26a1db target/riscv: fix use of uninitialized value
Scan-build reports:
	Logic error: Uninitialized argument value
	riscv.c:2688 2nd function call argument is an uninitialized value

This is a real error cause by running the command "riscv
authdata_write" without arguments. In such case 'value' is not
initialized and is passed to and used by r->authdata_write().

Reorganize the code to:
- detect the correct amount or command's arguments;
- drop the LOG_ERROR() on ERROR_COMMAND_SYNTAX_ERROR;
- drop the 'else' after 'return'.

Change-Id: I62e031220593b8308bc674b753e15d16d4c5c9ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7210
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-09-23 21:25:08 +00:00
Antonio Borneo fd2a44ab55 target/riscv: fix undefined operation
Scan-build reports:
	Logic error: Result of operation is garbage or undefined
	riscv.c:1614 The result of the left shift is undefined due
		to shifting by '4294967281', which is greater or
		equal to the width of type 'target_addr_t'

This is a false warning due to clang that considers the impossible
case of 32 bits hart (xlen = 32) in SATP_MODE_SV48 mode
(info->va_bits = 48).
Under such case:
	riscv.c:1614 ... ((target_addr_t)1 << (xlen - (info->va_bits - 1))) ...
the shift amount wraps around the unsigned type and assumes the
value 4294967281 (0xfffffff1).

Use assert() to prevent clang from complaining.

Change-Id: I08fdd2a806c350d061641e28cf15a51b397db099
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7209
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:24:49 +00:00
Antonio Borneo aff48a6a31 target/riscv: fix dead assignment
Scan-build reports:
	Unused code: Dead nested assignment
	riscv.c:459 Although the value stored to 'ir_user4_raw' is
		used in the enclosing expression, the value is
		never actually read from 'ir_user4_raw'

This is caused by the value reassigned in 'ir_user4_raw':
	riscv.c:459 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
but never used.

Drop the DIY conversion in favor of h_u32_to_le() that does not
reassign the input value.

Change-Id: Ifad29f4c46d4a2d0a2f5a5c4104d768cc3db2794
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7208
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:24:41 +00:00
Antonio Borneo ea9089944e target/riscv: fix unused initialization
Scan-build reports:
	Unused code: Dead assignment
	riscv.c:716 Value stored to 'result' is never read

Remove the initialization of variable 'result'.

Change-Id: Ied67bb4fcfa5bace186522074247ead43a5d5cd5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7207
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:24:34 +00:00
Antonio Borneo aa57890554 target/riscv-013: fix unused initialization
Scan-build reports:
	Unused code: Dead initialization
	riscv-013.c:2362 Value stored to 'control' during its
		initialization is never read

Remove the initialization of variable 'control'.

Change-Id: I548f8175530b9a2aa4c1788549d6467bf9824584
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7206
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:22:42 +00:00
Antonio Borneo 8db6dff333 target/riscv-013: fix unchecked return code
Scan-build complains about variable 'sbcs_orig' that can be used
not initialized.
	Logic error: Assigned value is garbage or undefined
	riscv-013.c:4468 Assigned value is garbage or undefined
This is caused by not checking the return value of the call
	riscv-013.c:4466 dmi_read(target, &sbcs_orig, DM_SBCS);
In fact when dmi_read() returns error, the variable 'sbcs_orig' is
not assigned.

Check the returned value.

Change-Id: Ia9032a0229aa243138f95f4e13f765726a4ceae9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7205
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:22:31 +00:00
Antonio Borneo 8683526af7 target/dsp563xx: fix scan-build warning
Scan-build triggers a warning:
	Unix API: Allocator sizeof operand mismatch
	dsp563xx.c:2143 Result of 'calloc' is converted to a pointer
		of type 'uint8_t', which is incompatible with sizeof
		 operand type 'uint32_t'

It's a false positive because calloc() is properly used in this
case, as the uint8_t array is used in blocks of 4 elements to read
or write uint32_t values.

Either
	calloc(sizeof(uint32_t), count);
and
	malloc(count * sizeof(uint32_t));
keep triggering the same warning.

Drop the warning by using the constant '4' as size of uint32_t, as
already used few lines below.

Change-Id: I5bb1ece177774eefdc5d9cd049338f8f2be87cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7203
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2022-09-23 21:22:09 +00:00
Tim Newsome 3c5be531df Don't use const on temporary variable.
It's not part of OpenOCD style:
https://review.openocd.org/c/openocd/+/6319/5..10/src/target/aarch64.c#b1500

Change-Id: Ifb612a942507ca5ed8cac3e3ec59e0e14b0298ed
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-22 09:59:15 -07:00
Tim Newsome b7738370b7 Make large if() more readable.
Change-Id: Ie43400387ab9f290e744ebaa09786612237e6c7e
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:48:09 -07:00
Tim Newsome fa1abc63d2
Add explanatory comment.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:44:10 -07:00
Tim Newsome 89746e111b
Fix comment indent.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:43:51 -07:00
Antonio Borneo 382148e4dd openocd: fix SPDX tag format for files .c
With the old checkpatch we cannot use the correct format for the
SPDX tags in the file .c, in fact the C99 comments are not allowed
and we had to use the block comment.

With the new checkpatch, let's switch to the correct SPDX format.

Change created automatically through the command:
	sed -i \
	's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \
	$(find src/ contrib/ -name \*.c)

Change-Id: I6da16506baa7af718947562505dd49606d124171
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7153
Tested-by: jenkins
2022-09-18 08:22:01 +00:00
Ian Thompson 61d0757acf target/xtensa: invalidate register cache on reset
Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: If7a4d00938fb188b008325249627f7773c3484c5
Reviewed-on: https://review.openocd.org/c/openocd/+/7197
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-18 08:12:02 +00:00
Ian Thompson 27e7f5df5f target/xtensa: fix clang analyzer warning
Reworked xtensa_queue_exec_ins_wide() logic to properly handle endian issues while executing arbitrary instructions.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I5752dd254ce8b8822886ffc7edecaa242a93cce8
Reviewed-on: https://review.openocd.org/c/openocd/+/7198
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-18 08:05:47 +00:00
Ian Thompson 4279b23fca target/xtensa: populate PS correctly during fetch
Read PS from EPS[debuglevel] during fetch such that it reflects the correct value when read via telnet (not just via gdb_server).

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I8504f68989bc6d5fe451a8cb69d01c86f4ec0100
Reviewed-on: https://review.openocd.org/c/openocd/+/7195
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-17 20:57:26 +00:00
Tim Newsome 4004db5d3a Make polling_interval unsigned.
Hopefully fixes win32 build.

Change-Id: I13d6d475f03bada96b2eb943f2c16df05413d34f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-16 16:52:11 -07:00
Tim Newsome 639e68a621 Make poll backoff time based.
Requested in https://review.openocd.org/c/openocd/+/6964.
I'm making the change here so I have a chance to test it properly before
pushing it upstream.

A nice effect of this change is that we avoid some unnecessary polling
early on when gdb is connecting and we would poll once every time we
send gdb a qXfer packet.

Change-Id: I4bdb9f05839e8c1e01ff6dde49d6589595418095
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-16 15:19:21 -07:00
Antonio Borneo cec3b62328 mips64: remove empty mips_mips64_soft_reset_halt()
The method soft_reset_halt is optional; no need to add an
empty function.

Remove mips_mips64_soft_reset_halt() and move the TODO comment
in struct target_type.

Change-Id: Id541a75e7a08645568961d59b73a120c2238701f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7184
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:19:13 +00:00
Ian Thompson 58bd387219 target/xtensa: fully initialize buffers for PWRSTAT read
Read buffer is sized for 32-bit APB version of PWRSTAT/PWRCTL registers. Initialize to zero so 8-bit JTAG register mirrors are accurate.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I81310649fa7180893d0188aab3c8a14315aaea0a
Reviewed-on: https://review.openocd.org/c/openocd/+/7183
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-13 22:18:57 +00:00
Antonio Borneo 5d6be673c3 target: don't export local symbols
Symbols that are not used outside the file should not be exported
and should be declared as static.

Change-Id: Icbe7f7bce287b903edec9dc9db3370722c51fbd5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7173
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:13:58 +00:00
Antonio Borneo 933cbd9156 riscv: don't export local symbols
Symbols that are not used outside the file should not be exported
and should be declared as static.
Move the existing comments to the static declarations.

Change-Id: Idf208e3fda4b3f8df789553cf03ebf5f20d811bb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7170
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
2022-09-13 22:12:29 +00:00
Antonio Borneo 07d84bca32 target: make local symbols static
Symbols that are not exported should be declared as static.

Change-Id: I2475524f4c14520e3163572560f4a9f276356ed5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7168
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:11:46 +00:00
Antonio Borneo a21489e9b9 xtensa: make local symbols static
Symbols that are not exported should be declared as static.

Change-Id: Ieb627f7f896e4663b0d5b18c4ab1853b39d23d03
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7167
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
2022-09-13 22:10:57 +00:00
Antonio Borneo 8310a238dc riscv: make local symbols static
Symbols that are not exported should be declared as static.

Change-Id: Ie3bd17535c8cb2a0fec5d3bedfe7de3e0a702613
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7166
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
2022-09-13 22:10:42 +00:00
Ian Thompson abe5f015c5 target/xtensa: fix step state transition
For some configurations, notably on DAP systems, resolve issue where single-stepping does not always transition into the HALTED state.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I053f4eaffad8c3228878ba87580ada640e4bd2fe
Reviewed-on: https://review.openocd.org/c/openocd/+/7150
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-13 22:09:02 +00:00
Ian Thompson b2b514be5b target/xtensa: enable DAP/SWD for generic xtensa
- Enable ADIv5 DAP systems via JTAG or SWD transport
- Select correct PWRCTL/PWRSTAT bits for XDM/APB

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I5894210c804f85075da868d0cfc6fb20b589d99f
Reviewed-on: https://review.openocd.org/c/openocd/+/7144
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-13 22:08:14 +00:00
Antonio Borneo 0c6e0bb82b openocd: remove CamelCase symbols *xPSR*
We have left the camelcase symbols *xPSR* for some time, to avoid
any conflict with possibly pending patches in gerrit.
With the approaching v0.12.0-rc1, it's time to revisit it.
The patches in gerrit that conflict with this rename are all not
merge-able due to conflicts or due to negative review.

Drop these CamelCase symbols.

Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7155
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:03:02 +00:00
Antonio Borneo de5c32fe23 openocd: remove recently added CamelCase symbols
Without the help of checkpatch, some CamelCase symbol passed
through the filter of maintainer's review.

Drop them.

Change-Id: If5fb07b2ffb89e853dd2a61f20d4134aa6e20d24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 48f267d4ad ("flash/stm32l4x: avoid using magic numbers for device ids")
Fixes: 5ab74bde06 ("semihosting: User defined operation, Tcl command exec on host")
Reviewed-on: https://review.openocd.org/c/openocd/+/7154
Tested-by: jenkins
2022-09-13 22:02:33 +00:00
Tim Newsome 8832d4be97 Add error message when dmstatus read times out.
Otherwise OpenOCD simply doesn't work without giving any indication why.

Change-Id: I21703fc1a0d9bed2f59da95f8a8395fe139484a4
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-13 10:18:39 -07:00
Tim Newsome 911d68ef25
Don't read dmcontrol to set hartsel (#723)
* Don't read dmcontrol to set hartsel

We already know what dmcontrol should be. This addresses a long-standing
TODO. In a toy test, this reduced the number of scans by 10+%. (Most of
those are probably in poll(), so don't actually affect perceived
performance.)

Change-Id: I18e5ca391f0f5fb35f30d44dfef834e5a66aee20
Signed-off-by: Tim Newsome <tim@sifive.com>

* Make code easier to read

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-09-09 09:57:39 -07:00
Ian Thompson de99836cf6 target/xtensa: virtualize XDM registers
Use indirect enum IDs to access XDM registers in preparation for supporting both NAR (JTAG) and APB (DAP).  No new clang static analysis warnings.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I0b742fe4661ff3cf609454b8650493d141a1e1ff
Reviewed-on: https://review.openocd.org/c/openocd/+/7143
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-08 09:32:23 +00:00
Erhan Kurubas bea4d65903 target/espressif: add semihosting support
ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-03 21:27:17 +00:00
iysheng 7dc4be3157 target/arm: Add support with identify STAR-MC1
Tested with an PLUS-F5270 board which uses the MM32F5277E9PV.

Signed-off-by: iysheng <iyysheng@gmail.com>
Change-Id: Icb75ae8337fdc6fa60e39d3d74dd8bc163707bdd
Reviewed-on: https://review.openocd.org/c/openocd/+/7136
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-03 21:26:20 +00:00
Tim Newsome a527112dae target/riscv: Update with latest encoding from riscv-opcodes
This gets us a clearly labeled BSD-3-Clause header, which should be
compatible with OpenOCD and Fedora, and also make it clear what the
license actually is.

See https://github.com/riscv/riscv-openocd/pull/710,
https://github.com/riscv/riscv-openocd/pull/713, and
https://github.com/riscv/riscv-openocd/pull/717.

Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7084
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-27 16:21:15 +00:00
Ian Thompson d93ac5482a target/xtensa: fix clang analyzer warnings
Scan-build of target/xtensa/ has no clang analyzer warnings from xtensa source files.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I11a125c923ece9a6fd0d9ee1698f742f88ee5cab
Reviewed-on: https://review.openocd.org/c/openocd/+/7141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-27 16:20:44 +00:00
Tim Newsome 7c0ca4dd53
Add copyright line to encoding.h. (#718)
Hopefully this will be the final version.

Change-Id: Ib2f8cd6f613c5e0f8e8bf7a16c3edbf2d9b439b2
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-25 11:04:46 -07:00
Tim Newsome 7a16947969
encoding.h license changed to BSD-3-Clause (#717)
See https://github.com/riscv/riscv-opcodes/pull/139

Change-Id: I77ae5ab369e6cde26ad44d177dcae38c0fbe08ef
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-22 08:56:44 -07:00
Erhan Kurubas f77c919cf4 target/xtensa: fix clang analyzer warnings and gcc12 build errors
Fix Unused code	Dead assignment at line 657
Fix Memory error Double free at line 2851
Fix Memory error Memory leak at line 2530
Fix error: 'a3' may be used uninitialized at line 758
Fix error: '%04x' directive writing between 4 and 8 bytes
into a region of size 5 at line 2471

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I0382a622bc7c4108a335fd741816577e79240397
Reviewed-on: https://review.openocd.org/c/openocd/+/7137
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-21 22:04:07 +00:00
Ian Thompson ce5ca9f7ba target: add generic Xtensa LX support
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file.  Not yet fully-featured.  Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support

Valgrind-clean, no new Clang analyzer warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-20 15:38:41 +00:00
Erhan Kurubas c271958850 target/semihosting: drop type casting from semihosting->result
Also used type helper (PRId64) to specify format of int64_t

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I594863eab594aff621c26fefcc69a1872e9730ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7111
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-20 15:27:46 +00:00
Tim Newsome fb523552d2
Update encoding.h again. (#713)
Now we get the license comment on the first line, which is required.

Change-Id: I54414db3c89ee6027e159ce9348459bc923b8595
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-18 10:10:49 -07:00
Erhan Kurubas 9cd714cd14 target/espressif: remove author lines from esp32xx and xtensa files
Some files have author info some doesn't. For the consistency we removed all.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie6f1ec012302e3a954c75c5106f12820722cb715
Reviewed-on: https://review.openocd.org/c/openocd/+/7104
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:27:10 +00:00
Tomas Vanek 3adbec9aab target/cortex_m: supress historical reset detection
The S_RESET_ST sticky bit is reset after DHCSR read.
It is set at power-on reset and keeps active until the debuger reads DHCSR.

Ignore S_RESET_ST at the very first read after OpenOCD start
and suppress possibly misleading message "external reset detected"
if we cannot guarantee the reset happened recently.

While on it add a TODO comment.

Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7109
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:23:57 +00:00
Ian Thompson 48db36f436 gdb_server: custom target-specific GDB queries
Provide a customizable hook for handling target-specific GDB queries

Valgrind-clean, no new Clang analyzer warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I684a259ed29f3651cbce668101cff421e522f79e
Reviewed-on: https://review.openocd.org/c/openocd/+/7082
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:23:05 +00:00
Antonio Borneo 0d56f379b5 target: add API to temporarily mask target polling
The same flag 'jtag_poll' is currently used as local data for the
command 'poll' and to temporarily mask the target polling.
This can cause unexpected behavior if the command 'poll' is
executed while polling is temporarily masked.

Add a new flag 'jtag_poll_en' to hold the temporarily mask
condition and keep 'jtag_poll' for the 'poll' command only.

While there, change the initial assignment of 'jtag_poll' using
the proper boolean value.

Change-Id: I18dcf7c65b07aefadf046caaa2fcd2d74fa6fbae
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7009
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2022-08-15 13:22:06 +00:00
Tim Newsome 81aa5fd6b4 target/riscv: Update debug_defines.h.
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.

See https://github.com/riscv/riscv-openocd/pull/711

Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7087
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:18:16 +00:00
Tomas Vanek 0e1fe03f4b target/arm: do not expose 'arm reg', 'arm mcr/mrc' commands on Cortex-M
Tcl commands 'arm reg', 'arm mcr/mrc' do not work on M-profile based devices.
Isolate them from 'arm core_state' and 'arm disassemble' and do not chain
them from armv7m_command_handlers.

Change-Id: I2c6befdf82575e95cf05ed158ab5e6faa1a182c3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7101
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-08-14 14:43:48 +00:00
Tomas Vanek dee7b7d821 target/arm: make 'arm core_state' command compatible with Cortex-M
Tcl command 'arm core_state' was exposed even on Cortex-M devices.
However it returned message "Unsupported Command" without error status
on such device.

Set the only possible arm->core_state ARM_STATE_THUMB in armv7m init.
Block setting core_state to arm on Cortex-M.

Change-Id: I9525553ac8863a6cf77bbacbcd57e354b6cfe1ca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7100
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-08-14 14:43:04 +00:00
Tomas Vanek b6dad912b8 target/cortex_m: prevent segmentation fault in cortex_m_poll()
If a Cortex-M MCU become unresponsive during a debug session and
re-examination fails to find MEM-AP, debug_ap pointer is set to NULL.

Eventual call of cortex_m_poll() dereferences debug_ap.

Check debug_ap validity at the begin of cortex_m_poll().

Change-Id: I9519f48760c91a48a9e5e8c34634d247098cb14a
Fixes: 35a503b08d (arm_adi_v5: add ap refcount and add get/put around ap use)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7108
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-14 12:11:26 +00:00
Tomas Vanek cae0c8b32b target: move parent target structs just after common_magic
Just a cosmetic refactoring.

Change-Id: I7fbc05324e346fafc98d1b42691d33d3d8fbd04e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7003
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-08-14 12:10:14 +00:00
Tomas Vanek ea49b2b2a2 target/aarch64: fix duplicate common magic
AARCH64_COMMON_MAGIC was same as CORTEX_A_COMMON_MAGIC, probably copy pasta.
Define unique AARCH64_COMMON_MAGIC

Change-Id: Ie30e0028453a1fce5624ecad9bf73d5ac3791281
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6997
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-14 12:03:23 +00:00
Tomas Vanek 8f299c6aec target: consolidate existing target/algo common_magic
Unify common_magic type to unsigned int
Move common_magic to be the first member of the struct
Add unsigned specifier to xxx_COMMON_MAGIC #defines

Change-Id: If961d33232698529514ba3720e04418baf6dc6fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6996
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-14 12:02:38 +00:00
Tomas Vanek 2aaa991a50 target: fix unaligned return of target_get_working_area_avail()
The working area allocation routines use 4 byte word alignment.
In the corner case the size of the working area is not aligned,
target_alloc_working_area() of size = target_get_working_area_avail()
will fail because the size gets aligned up and does not fit to the area
which size is aligned down.

Align down the result of target_get_working_area_avail() to cope with that
corner case.

While on it use fancy ALIGN_... macros instead of bitwise and operator.

Change-Id: Ia2a1e861c401c2c78fe6323379a3776fb4f47b06
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7096
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-08 20:51:52 +00:00
Tomas Vanek b5dd6faf8d target/cortex_a: remove unused CORTEX_A15_COMMON_MAGIC
Change-Id: I7dddc6cb7b0ee8aec7164998f1124b522e899f3d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7099
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-08 19:59:22 +00:00
Evgeniy Naydanov 52177592f9
Fix overflow issue in write_memory_progbuf (#714)
If range's upper bound was equal to 2^64 or the range was wrapping around 0
(which is perfectly legal), writes were not performed due to riscv_addr_t
overflow.
2022-08-01 08:46:36 -07:00
Tomas Vanek 1d8bc131a6 target/riscv: add common magic
Add common_magic member to struct riscv_info.
Introduce is_riscv() helper.

Change-Id: I1af05988ad869342ba5dc6d4d0ba0ec6a8bf7bc7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6999
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-08-01 08:58:02 +00:00
Tomas Vanek 82e76262a1 target/riscv: use struct riscv_info instead of typedef riscv_info_t
Make the main RISC-V structure more compliant with OpenOCD coding style.
Other typedefs remains as is.

Change-Id: I5657ad28fea8108fd66ab27b2dfe1c868dc5805b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6998
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-08-01 08:57:41 +00:00
Ben Bender 2c6571b9b1 arm_adi_v5: Adding Nuvoton NPCX quirk
We found that the NPCX has an issue with the byte lanes so that non byte
aligned writes aren't working. To overcome this, for byte accesses we
copy the byte to be written to all of the byte lanes.

doc: Document command nu_npcx_quirks

Signed-off-by: benjbender <benjbender@gmail.com>
[Andreas Fritiofson: Squashed commits]
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change-Id: I9ef63bf692f4e68f57459e1ec33f3abcbf533cd2
Reviewed-on: https://review.openocd.org/c/openocd/+/6630
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-30 08:49:47 +00:00
Tim Newsome 793def24c5
Properly set dmcs2.grouptype. (#712)
In #697 this had gotten inverted.

Change-Id: Id86e2cfee0d15c1f05846c1fd5ac83dde26575a2
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-25 15:54:49 -07:00
Erhan Kurubas 49cf334e98 target/semihosting: export semihosting_common_handlers[] from header file
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I4add0c1dc7888497ee90fd02754607a16434b66f
Reviewed-on: https://review.openocd.org/c/openocd/+/7075
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-23 14:00:26 +00:00
Antonio Borneo 057e566097 openocd: src/target: replace the GPL-2.0-or-later license tag
Replace the FSF boilerplate with the SPDX tag.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7071
Tested-by: jenkins
2022-07-23 13:58:51 +00:00
Antonio Borneo c3d3487d61 openocd: src: fix incorrect SPDX tags
The SPDX tag is aimed at machine handling and it's thus expected
to be placed in the first line in specific format.

Move the SPDX tag to the first line and fix it where needed.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: Ie9a05f530009d482a4116eebd147fd7e1ee3d41e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7066
Tested-by: jenkins
2022-07-23 13:16:09 +00:00
Antonio Borneo 5635fbc25a openocd: src: replace the incomplete GPL-2.0-or-later license tag
Few files have the FSF boilerplate without the latest statement on
where to get the GPL license.

Manually replace the FSF boilerplate with the SPDX tag.
While there, reorganize the copyright statement.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: I0c908d01c010e24f9c7e94885e7fbed4ecf26a86
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7063
Tested-by: jenkins
2022-07-23 13:15:24 +00:00
Antonio Borneo db0d4dbc3f openocd: src: add GPL license tag on files that miss it
Some file miss completely the license tag.

Add the SPDX tag, using the same GPL-2.0-or-later license of the
OpenOCD project.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: I1fb51e722232d14f050458a820c3041de3dc9138
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7058
Tested-by: jenkins
2022-07-23 13:13:39 +00:00
Antonio Borneo dba88e0238 openocd: src: remove duplicated GPL license tag
SPDX tag is replacing the FSF boilerplate.
For files that have both, remove the FSF boilerplate and keep only
the SPDX tag.

Change-Id: I04c4764d13d4ca92453f30ed16aeae53cd4c3fc8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7057
Tested-by: jenkins
2022-07-23 13:07:57 +00:00
Antonio Borneo 96202cda19 openocd: build: add SPDX tag
Add the SPDX tag to makefiles, configuration scripts and tcl files
present in the folders under src/

Change-Id: I1e4552aafe46ef4893d510da9d732c5f181784a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7051
Tested-by: jenkins
2022-07-23 13:06:38 +00:00
Tim Newsome 969f112321
Update debug_defines.h. (#711)
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.

Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-18 09:20:22 -07:00
Tim Newsome aaf0620479
Update with latest encoding from riscv-opcodes (#710)
This gets us the new license header, which was requested upstream.

Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-08 13:02:13 -07:00
Pavel Kirienko 5e96b012af semihosting: fix return value of SYS_READ and SYS_WRITE
ARM/RISC-V semihosting calls SYS_READ/SYS_WRITE require
inversion of the result value as described in
"Semihosting for AArch32 and AArch64". Prior to
this patch, this was done correctly only if
(semihosting->is_fileio==false).

This patch has been tested with STM32F446.

Change-Id: I1b34c8d8393f7dfa66ee6539904a2eaf8f9154b0
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/232/
Reviewed-on: https://review.openocd.org/c/openocd/+/6803
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-02 08:28:30 +00:00
Antonio Borneo b7125c369c target: esp_xtensa_smp: fix clang report
The variable 'smp_break' is only set and used in case of smp.
But clang cannot track if 'target->smp' get modified between the
set and the use of 'smp_break', so it consider possible to use
'smp_break' uninitialized.

Initialize 'smp_break' to silent clang.

Change-Id: Ifa25a84fe9ffa25b8b58d7920ec77994c3b7ebfe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 77287b8d47 ("target: add Espressif ESP32 basic support")
Reviewed-on: https://review.openocd.org/c/openocd/+/7050
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
2022-07-02 08:27:31 +00:00
Erhan Kurubas 06c3240155 semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h
These enum values are useful for the arch level semihosting call handlers.
Currently riscv uses them, we also need similar return codes for the xtensa.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I8f63749cc203c59b07862f33edf3c393cd7e33a9
Reviewed-on: https://review.openocd.org/c/openocd/+/7039
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-02 08:27:12 +00:00
Antonio Borneo 717b99164a semihosting: remove comparison with NULL
Commit b9526f1401 ("semihosting: permit redirection of
semihosting I/O to TCP") introduces a new comparison with NULL.

Remove it.

Change-Id: Ice4333c50d16f7592f0ff86b1640217fa42e34f6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b9526f1401 ("semihosting: permit redirection of semihosting I/O to TCP")
Reviewed-on: https://review.openocd.org/c/openocd/+/7031
Tested-by: jenkins
2022-06-24 21:50:41 +00:00
Antonio Borneo e4f5ce5d3e aarch64: fix handling of 'reset halt'
Commit 6c0151623c ("aarch64: add support for "reset halt"")
introduces the register setting to halt at reset vector, but:
- does not consider the case 'srst_pulls_trst' that makes useless
  setting the registers as they will be erased by the pulled trst;
- does not clean sticky errors in case of 'srst_gates_jtag'.

Avoid any register initialization on 'srst_pulls_trst' and move
the cleaning of sticky errors in the common block.

Change-Id: I6f839f06f7b091e234ede31ec18096e51f017bcd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 6c0151623c ("aarch64: add support for "reset halt"")
Reviewed-on: https://review.openocd.org/c/openocd/+/7034
Tested-by: jenkins
Reviewed-by: Christian Hoff <christian.hoff@advantest.com>
2022-06-24 21:49:25 +00:00
Erhan Kurubas 334a187e64 semihosting: add custom user command handler
Custom user syscalls can be handled with target events in the TCL scripts.
This patch gives another opportunity to handle custom syscalls in the c files.
Besides that some utility functions are also exported for the custom handlers.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ice13d527540a0de0b2a8abda912ae3dcff3834b7
Reviewed-on: https://review.openocd.org/c/openocd/+/6889
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24 21:47:43 +00:00
Erhan Kurubas af9daf4433 esp32s2: convert counted timeout to timeval_ms
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Id685408281478cec0e7e886dbedb3b8972c7b652
Reviewed-on: https://review.openocd.org/c/openocd/+/7020
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
2022-06-24 21:47:07 +00:00
Erhan Kurubas 2053120ba1 target: add Espressif ESP32-S3 basic support
ESP32-S3 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
Reviewed-on: https://review.openocd.org/c/openocd/+/6990
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24 21:46:42 +00:00
Erhan Kurubas 77287b8d47 target: add Espressif ESP32 basic support
ESP32 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
Reviewed-on: https://review.openocd.org/c/openocd/+/6989
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24 21:46:07 +00:00
Antonio Borneo c28ae626a2 arm_adi_v5: parse ROM tables behind SoC-600 APv1 adapter
Arm "CoreSight System-on-Chip SoC-600" specification describes a
bridge "Access Port v1 adapter" aimed to "connect a legacy Access
Port (AP) ... into an CoreSight Architecture v3 system".

A ROM table can be located in the "legacy" part of the system,
on the legacy AP behind the APv1 adapter.

For the purpose of scanning the ROM tables, consider an ADIv6
SoC-600 APv1 adapter as an ADIv5 AP.

Change-Id: I97d42fb77013c1251fb68d0caa4274086bf38a70
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6827
Tested-by: jenkins
2022-06-24 21:39:39 +00:00
Antonio Borneo 1842cf69a9 adiv6: stay in same AP during dap_lookup_cs_component()
Configuration file can specify, as target's debug AP, an AP that
contains a ROM table that points, in turn, to other APs.
Current code in cortex_a and aarch64 is not able to handle a
return from dap_lookup_cs_component() that points to another AP.

While it could be interesting to specify 'root' as target's debug
AP, drop any found value if it's not in the starting AP.

Change-Id: Id206e4fa7a29e9402c8e2393026817b410bbb8bd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6826
Tested-by: jenkins
2022-06-24 21:39:16 +00:00
Antonio Borneo 9f0ac0e6bb adiv6: add support for ROM tables in AP
ADIv6 adds AP that only contain a ROM table in the AP itself, that
can point to other AP containing either another AP level ROM table
or a MEM-AP to be parsed as usual.

Add support for parsing AP level ROM tables.

Change-Id: Ic25863b16463b8a6adc3b15e26db7fdca858d6df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6467
Tested-by: jenkins
2022-06-24 21:38:52 +00:00
Antonio Borneo b987a419b4 adiv6: prepare for AP level ROM tables
ADIv6 adds AP that only contain a ROM table in the AP itself, that
can point to other AP containing either another AP level ROM table
or a MEM-AP to be parsed as usual.

To handle recursive AP access, reorganize the code to:
- pass the depth==0 from the command 'dap info';
- print the AP number as first line, adding proper indentation on
  depth>0;
- align the following print with proper indentation.

Change-Id: I5b811810c807fc51b307bd60f67817d9de2aa095
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6466
Tested-by: jenkins
2022-06-24 21:38:30 +00:00
Antonio Borneo 8c1d518232 arm_adi_v5: add option 'root' to 'dap info' command
On ADIv6 the system root ROM table is found by reading the DAP DP
registers BASEPTR0 and BASEPTR1.

Add option 'root' to the commands 'dap info' to let it retrieve
the system root ROM table's AP from DAP DP, then use such AP for
following dump.

Change-Id: I1789457a005faa3870c5d14f763378d2f6a5f095
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6462
Tested-by: jenkins
2022-06-24 21:38:08 +00:00
Antonio Borneo 3f4bc6ce7f adiv6: use struct adiv5_ap->ap_num to contain the AP base address
ADIv5 DAP can only have 256 AP, while ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.

Reuse the field ap_num in struct adiv5_ap, currently used on ADIv5
to hold the ADIv5 AP number (apsel), to contain the ADIv6 AP base
address.

Convert struct adiv5_ap->ap_num to 64 bit and initialize it to
DP_APSEL_INVALID for unused AP.
Restrict dap_find_get_ap() to ADIv5 only. To be enhanced.
On ADIv6, let dap_get_ap() return an already allocated AP, or
allocate and return an unused AP.
Add function is_ap_num_valid() and use it.

Change-Id: Ib2fe8c7ec0d08393cd91c29fdac5d632dfc1e438
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6461
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
2022-06-24 21:37:44 +00:00
Antonio Borneo 72fb88613f adiv6: add low level swd transport
During enter in SWD read DP_DPIDR without selecting the register
bank through DP_SELECT_DPBANK.
Handle the different format of DP_SELECT register.

Change-Id: Iea1b8eb6ec94177e16a430d5885595a38e833eeb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6697
Tested-by: jenkins
2022-06-24 21:37:21 +00:00
Kevin Burke 62058c0a32 adi_v5_jtag: extend memaccess_tck to every AP access
ADIv5 reports:
	Accessing AP registers or debug resources in connected
	device through an AP can be subjected to other variable
	response delays in the system. A debugger that can adapt
	to these delays and avoid wasting WAIT scans operates more
	efficiently and provides higher maximum data throughput.

The existing code in OpenOCD uses extra tck only for accessing
resources through an AP.

Extend the use of extra tck also for accessing an AP register.

Split from change https://review.openocd.org/6077/

Change-Id: I2082362e098d09f4ba0668e01f5196afc965c8f3
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6460
Tested-by: jenkins
2022-06-24 21:37:00 +00:00
Kevin Burke 8f8fb0fa79 adiv6: add low level jtag transport
swd and dap-direct are not implemented yet

Split from change https://review.openocd.org/6077/

Change-Id: I6d73d8adf6a6090001c5d4771325fb1d63c45e3c
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6459
Tested-by: jenkins
2022-06-24 21:35:46 +00:00
Antonio Borneo edb575800a adi_v5_jtag: clear sticky overrun error
By accessing invalid AP in JTAG mode, it's possible to trigger the
error:
	JTAG-DP STICKY ERROR
After that the sticky error is never cleared and the whole DAP
gets not anymore accessible.

Clean-up the sticky error once detected.

Change-Id: I8b07263b30f9e46645f0c29084b8f1626e241f45
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6430
Tested-by: jenkins
2022-06-24 21:35:27 +00:00
Kevin Burke 513aba1930 adiv6: read ROM Table address size
Required for parsing ADIv6 ROM tables.

Split from change https://review.openocd.org/6077/

Change-Id: I849543b7b4a4455b10bd9fc7da38a37849d71700
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6458
Tested-by: jenkins
2022-06-24 21:35:08 +00:00
Kevin Burke a6e4aabc66 adiv6: re-organize mem_ap registers definition
ADIv5 MEM-AP registers are a subset of ADIv6 MEM-AP registers and
are located at different offset.

To prepare for introducing ADIv6, add 'struct adiv5_dap *' as
argument to ADIv5 registers macro.
Check the ADI version and use the proper address.
Both adapter drivers rshim and stlink are ADIv5 only, so let them
use the ADIv5 macros only.

Split from change https://review.openocd.org/6077/

Change-Id: Ib861ddcdab74637b2082cc9f2612dea0007d77b1
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6457
Tested-by: jenkins
2022-06-24 21:34:51 +00:00
Kevin Burke 1fe82f9f1d adiv6: add dap flags -adiv5 and -adiv6
Add flags to 'dap create' command and set the field adi_version
in struct adiv5_dap.

Actually only ADIv5 is functional. Other patches are needed to get
ADIv6 working.

Split from change https://review.openocd.org/6077/

Change-Id: I63d3902f99a7f139c15ee4e07c19eae9ed4534b9
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6456
Tested-by: jenkins
2022-06-24 21:34:30 +00:00
Antonio Borneo 35a503b08d arm_adi_v5: add ap refcount and add get/put around ap use
While an ADIv5 DAP can only have 256 AP, ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.
The actual trivial code implementation for ADIv5 (that uses an
array of 256 ap in the struct adiv5_dap) cannot be extended as-is
to handle ADIv6.

The simple array of 256 AP can be reused as a dynamic storage for
ADIv6 ap:
- the ADIv5 AP number is replaced by the ADIv6 base address;
- the index of the array (equal to ADIv5 AP number) has no link to
  any ADIv6 property;
- the ADIv6 base_address has to be searched in the array of AP.

The 256 elements in the AP array should be enough for any device
available today. In future it can be easily increased, if needed.

To efficiently use the 256 elements in the AP array, the code
should associate one element of the array to an ADIv6 AP (through
the AP base address), then cancel the association when the AP is
not anymore needed. This is important to avoid saturating the AP
array while exploring the device through 'dap apreg' commands.

Add a reference counter in the struct adiv5_ap to track how many
times the struct has been associated with the same base address.
Introduce the function dap_get_ap() to associate and return the
struct, and dap_put_ap() to release the struct. For the moment the
code covers ADIv5 only, so the association is through the index.
Use the two functions above and dap_find_get_ap() throughout the
code.
Check the return value of dap_get_ap(). It is always not NULL in
the current ADIv5-only implementation, but can be NULL for ADIv6
when there are no more available AP in the array.
Instrument dap_queue_ap_read() and dap_queue_ap_write() to log an
error message if the AP has reference counter zero, meaning that
the AP has not been 'get' yet. This helps identifying AP used
without get/put, e.g. code missed by this patch, or merged later.
Instrument dap_cleanup_all() to log an error message if an AP has
reference counter not zero at openocd exit, meaning that the AP
has not been 'put' yet.

Change-Id: I98316eb42b9f3d9c9bbbb6c73b1091b53f629092
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6455
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
2022-06-24 21:33:23 +00:00
Jan Matyas 6d359afde4
Fix: Prevent segfault in riscv_invalidate_register_cache for non-examined targets. (#692)
The segfault could be triggered if:

- At least one target failed to get examined (therefore does not have the
  register cache set up yet),

- and "reset" TCL command was issued, which internally tries to
  invalidate the register cache.

Minor cleanup: "registers_initialized" member removed from riscv_info_t
because it is not used anywhere.

Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-06-16 09:58:45 -07:00
Tim Newsome d85a4e8098
Remove unused code. (#707)
Change-Id: I3961a62c0c51200ff3241265d9ea3e69492bdc4e
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-06-15 10:22:19 -07:00
Erhan Kurubas 480d4e1772 semihosting: fix accessing memory outside the bounds of the fn array
There is an accsess to wrong index, when arm semihosting_basedir
command not used or basedir set to empty string.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I3afa049d74b30496f5c03ba4ef67431784f81bdc
Fixes: ce5027ab01 ("semihosting: add semihosting_basedir command")
Reviewed-on: https://review.openocd.org/c/openocd/+/7005
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-10 21:56:47 +00:00
Antonio Borneo 7cc79a8d62 arm_adi_v5: check for calloc() return value
In function adiv5_jim_configure() check that calloc() returns a
valid allocated memory pointer.

Change-Id: I97287e168834693900341add9d9eb9a5f38c55b4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7014
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:55 +00:00
Antonio Borneo 95135b39cc arm_adi_v5: fix scan-build warning [3/3]
While scan-build complains that dap_p or ap_num_p could be NULL,
the current code never passes NULL pointers.
Add an assert() to silent scan-build and prevent any further use
of the function with incorrect parameters.

Change-Id: I656810dddcea61e85d85b13efb114f7607ef837c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7012
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:29 +00:00
Antonio Borneo aee7c70a1a arm_adi_v5: fix scan-build warning [2/3]
Commit d01b3d69ec ("arm_adi_v5: separate ROM table parsing from
command output [3/3]") introduces a new scan-build warning because
removing one return in case of error causes using uninitialized
values.

Add back the return on error.

Change-Id: I10ddc548b756d34aaccc0511f091b4caa5ec271a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: d01b3d69ec ("arm_adi_v5: separate ROM table parsing from command output [3/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7011
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:17 +00:00
Antonio Borneo 63e22d5fb9 arm_adi_v5: fix scan-build warning [1/3]
Commit 21f7885d1c ("arm_adi_v5: separate ROM table parsing from
command output [1/3]") introduces a new scan-build warning because
continues the execution even when dap_get_debugbase() returns
error. The value of 'apid' can be uninitialized:

	5th function call argument is an uninitialized value

Check the return value and quit on error.
While there, remove the useless initialization of 'dbgbase' that
was apparently required for the same problem.

Change-Id: Iade26a152925ee0f1bf114ed829b94f7ed5b254f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 21f7885d1c ("arm_adi_v5: separate ROM table parsing from command output [1/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7010
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:01 +00:00
Tomas Vanek 7e9e5dca07 target/riscv: drop unused variable registers_initialized
Change-Id: If7bfe38ac273ce9e54003e003807e128cced1568
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6995
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-04 08:20:09 +00:00
Erhan Kurubas 78c87f5e81 target: add Espressif ESP32-S2 basic support
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-06-04 08:18:44 +00:00
Tarek BOCHKATI b470b664ca cortex_a: get rid of not needed log messages
when using semi-hosting with cortex_a this LOG_INFO pollutes openocd
console, so just reduce the log level of this message.

Change-Id: I91aa70492f4e361b25a0e5517d0cf73f2f8ed599
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://gerrit.st.com/c/stm32ide/official/openocd/+/248225
Tested-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6993
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-03 23:46:21 +00:00
Tomas Vanek cc8b491856 flash/nor/core, target: don't ask for working mem if no target algo
The command 'flash erase_check' showed the message
'Running slow fallback erase check - add working memory'
even in the case the target didn't implement blank_check_memory.

Change return code of target_blank_check_memory() in this case
and sense it in default_flash_blank_check() and show a message
without a request for working memory.

Change-Id: I7cf9bf77742964b4f377c9ce48ca689e57d0882f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6765
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-05-29 15:47:21 +00:00
Tim Newsome bce93f6d51 Give each SMP group a unique number.
This helps e.g. if there are 8 cores, and cores 0--3 are in one SMP
group while 4--7 are in another group. (And there are 2 gdb instances
connected, one debugging the first group, and one the second.)

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7b6c9382eadf964529105eaf0411a42d48768668
Reviewed-on: https://review.openocd.org/c/openocd/+/6979
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-27 22:52:35 +00:00
Tim Newsome 5c34da1415
Use new debug_defines.h (#703)
* Update debug_defines from the spec.

Now it includes constants for field values, so use them instead of
duplicating that here.

Change-Id: I2fca6e89f25123c39d4bf483b8244e47aefb0f88

* Remove unused #defines

Change-Id: Id20351851c9ed2c3aa82ccf8c04b604bef11692a

* Use debug spec constants in a few more places

Change-Id: Ic4578729c89e3c6a26a72772e1635c5345bd6a52
Signed-off-by: Tim Newsome <tim@sifive.com>

* Use macros for trigger action types.

Which were added with the very latest debug_defines.h.

Change-Id: I47f73e11d2ec529c720f2e1df05f7b0d3026e43a
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-05-25 10:08:43 -07:00
Erhan Kurubas ce5027ab01 semihosting: add semihosting_basedir command
This command allows users to set base working directory for the
semihosting I/O operations.Default is the current OpenOCD directory.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I80c5979e4c96d66cccdd12cc6fcd5f353e5c6b4d
Reviewed-on: https://review.openocd.org/c/openocd/+/6888
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-21 09:01:56 +00:00
Tomas Vanek 0f11f951e7 target: fix clang static analyzer warning
Removes Warning:	line 6482, column 12
1st function call argument is an uninitialized value

Use target ptr directly as checked in previous lines instead of
dereferencing head->target

Change-Id: I6804b776fd493af71f3098d702f9cdc7acb50151
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6970
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-21 09:00:05 +00:00
Tim Newsome 0fada02494
Correctly set target->smp. (#701)
This was broken by #684. Thanks to Jan for noticing.

Change-Id: I6ce115a6a333b93d7edb3ee44daae3f618d092e6
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-05-18 09:40:22 -07:00
Tomas Vanek 7d2ea186cf target/riscv: fix 'reset run' after 'reset halt'
'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
If hw reset line is configured e.g. 'reset_config srst_only'
the folowing 'reset run' halts:

 > gd32v.cpu curstate
 running

 > reset halt
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted <<<<---- wrong!!!

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 running

Clear DM_DMCONTROL_HALTREQ when acking reset.

Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6961
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-05-18 09:03:41 +00:00
Tim Newsome 6047fedc63
Change set_haltgroup() to more general set_group() (#697)
* Change set_haltgroup() to more general set_group()

Change-Id: Ib91a252ac63604e54b756f70c549ccd47241fd10
Signed-off-by: Tim Newsome <tim@sifive.com>

* Properly use enum.

Change-Id: I0edef6053fac388db38a22fe7557623fa93ec705
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>

* Style changes suggested in review.

Change-Id: I29e83d3dbef09cb971ec0355aff733191a6e4679
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-05-16 10:17:04 -07:00
wzgpeter a408bdc8db
fix: semihosting_fileio display the unsupported info (#699)
the abnormal info display below:
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0

the PC did not plus 4 before resume, which cause this
abnormal info popup.

Change-Id: I15c1e7426f1925e78f607c566976f9352216506f
Signed-off-by: Wu Zhigang <zhigang.wu@starfivetech.com>

Co-authored-by: Wu Zhigang <zhigang.wu@starfivetech.com>
2022-05-16 09:57:22 -07:00
Antonio Borneo 99293ebd15 aarch64: don't wait for smp targets halted in deassert reset
The function target_type::deassert_reset() is called for every
target after reset is deasserted. If the target fails to get
halted, we log a warning and issue a halt request for the target
itself.

Current code calls the generic target_halt() that:
- extends the halt to all the targets in the SMP node;
- waits for targets to halt.
This breaks the logic of running target_type::deassert_reset()
per target. Plus, waiting for targets to halt delays the call of
target_type::deassert_reset() for the next targets.

Replace the call to target_halt() with the aarch64 specific
function to halt the single target. Pass the parameter HALT_LAZY
to prevent the wait for target halted.
Similar solution is already implemented for cortex_a.

Change-Id: I446dc03cb91524c6d388db485bc2388177af77b6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6947
Tested-by: jenkins
2022-05-14 08:57:36 +00:00
Antonio Borneo a47d1f1b79 arm_adi_v5: add support for 64bit Class 0x9 ROM tables
Arm documentation does not explicitly report the order of the two
32bit words that compose the 64bit value. But both ADIv5 and ADIv6
specify that only little-endian is supported (ADIv5.2 obsoletes
the big-endian support). This change reads the 64bit value in
little-endian.

Detect the 64bit content and use it.

Change-Id: I723ec099c7e8c70c1f9a568e32ea867fcbf1f1db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6465
Tested-by: jenkins
2022-05-14 08:56:37 +00:00
Antonio Borneo d74f11dcd4 arm_adi_v5: replace dap_lookup_cs_component()
With the generic function for ROM table walk-through, reimplement
dap_lookup_cs_component().

Catch the code CORESIGHT_COMPONENT_FOUND and halt the search.
While there, drop two macros in arm_coresight.h, now unused.

Change-Id: I589ef7ae8a651d0c422ce7d0b4ed913713a8217e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6824
Tested-by: jenkins
2022-05-14 08:55:52 +00:00
Antonio Borneo 613f1c6abb arm_adi_v5: let dap_lookup_cs_component() to get AP dbgbase
Simplify the code in cortex_a and aarch64 by moving the call to
dap_get_debugbase() inside dap_lookup_cs_component().

This has the further effects:
- dap_get_debugbase() is not referenced outside arm_adi_v5.c and
  becomes static;
- dap_lookup_cs_component() looses one parameter;
- the coreid parameter 'idx' is passed as value;
- the caller in aarch64 don't have and don't print the irrelevant
  value of AP register APID;
- fixes the debug message in the caller in aarch64 to print the
  coreid value instead of always zero.

Change-Id: Ic7f0f643fdf067c059c8f2455a02ff18a3fed054
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6823
Tested-by: jenkins
2022-05-14 08:55:33 +00:00
Antonio Borneo 7351330a0f arm_adi_v5: abstract actions during ROM table parsing
Now all the actions (build command output) of command "dap info"
are decoupled from the ROM walk-through.
Pass the actions as a generic parameter to ROM walk-through code.
Put as private data every information that is only required by the
actions and not by the ROM walk-through.

Change-Id: I3b6ad112ea21296458c94aebbf91bf65bf6657a7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6822
Tested-by: jenkins
2022-05-14 08:54:53 +00:00
Antonio Borneo d01b3d69ec arm_adi_v5: separate ROM table parsing from command output [3/3]
This change only targets the output of rtp_rom_loop().

Change-Id: If9ac013798923428c3b897a969887e98b6935a2b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6821
Tested-by: jenkins
2022-05-14 08:54:36 +00:00