We can't actually accept data during reset, so don't assert ready.
Modify the testbench to try to send data while the core is reset, so we
can verify that it doesn't get accepted.
Fixes: 52325f2 ("Add AXI stream replay buffer")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The OUI in the PHY ID is "bit-reversed," AKA each byte is bit reversed,
but the overall order is the same. This is a bit more complex than I
initially thought. Fix the mapping, and use a non-zero OUI for testing.
Fixes: d9602b6 ("Add MII management functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add an option to register the wishbone busses post-mux. This can help
achieve timing, since the phys are often in different parts of the FPGA.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This module registers all signals on a wishbone bus. This increases
latency/decreases throughput, but the wishbone cores here are just for
management, so that's not really critical.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The counters in this module end up on the critical path a lot. The
counters themselves take 3-4 ns to compute, but routing the increment
signal to the counter eats up a lot of slack. Register the increment signal
for a clock to let it cross the FPGA without affecting the counter timing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
ack/err can only be combinatorial if data_read is also combinatorial.
I suspect doing that will kill my Fmax, so register ack/err.
Fixes: d9602b6 ("Add MII management functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add a reset synchronizer to ensure synchronous reset release. There is
also a glitch filter to reject spurious resets. It will reject pulses
shorter than 5 ns (or around 1.25 ns per LUT).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add a basic bridge for debugging. It's around 50% efficient, but this
could be increased to 66% with the addition of some FIFOs. The limiting
factor is the constant overhead of the request/status bytes. If we used
a wider bus, we could get better efficiency.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Handshaking happens on the rising edge based on the current values of
ready/valid. Fix the current (incorrect) logic. Additionally, modify the
testbench to properly stimulate AXI stream cores. This will catch
several handshaking failures fixed in previous commits.
Fixes: 52325f2 ("Add AXI stream replay buffer")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
AXI stream data is transferred based on the current values of the signals,
not the previous ones. This will cause problems if the other end isn't
valid all the time. Fix this, and amend the testbench to test it.
Fixes: e44d381 ("Add UART transmit module")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Since cocotb/cocotb#2793, writes happen before the clock instead of
after the clock. This breaks the collision test, since we test for
differing behavior over a difference of 1 ns. Fix the failure by
applying an adjustment for newer versions.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
signal_status and must be low for a rising edge before it goes high. At
the moment we depend on ClockEnable to wait for a rising edge. Instead,
wait for a falling edge explicitly. This makes this test less
dependent on how tx_ce is generated.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
AXI stream is transferred exactly on the rising edge of the clock. Use
the current value of the signals for this, instead of past values.
Simulate a slower slave to ensure this is tested.
Fixes: a549fca ("Add UART receive module")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The AXI stream master doesn't cope with slaves that aren't ready all the
time. There are two separate issues: first, the data was only valid for one
cycle. Second, the handshake logic was incorrect. Rectify these, and modify
the testbench to test for this condition.
Fixes: 7514231 ("Add AXIS-Wishbone bridge")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds the core of the UART-Wishbone bridge. The protocol has
a variable-length address phase to help reduce overhead. Multiple
in-flight commands are not supported, although this could be resolved
with some FIFOs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Signals modified by cocotb tasks may not be visible to other tasks on
the same clock cycle. This was causing issues for recv_packet, because
it might not see the same values for ready/valid driven by ClockEnable
that the DUT sees. This was worked around by sampling on the RisingEdge.
However, this can cause recv_packet to miss data. Fix this by using
RisingEdge for ClockEnable, so everything can be sampled on the
FallingEdge.
Fixes: 52325f2 ("Add AXI stream replay buffer")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add the recieve half of the UART. It's more or less the inverse of the
transmit half, except we manage the state explicitly. I originally did
this in hopes that yosys would recode the FSM, but it doesn't like the
subtraction in the D* states. I left in the async reset anyway since it
reduces the LUT count.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Export recv_packet for use by other testbenches. This is mostly
straightforward, except we need the ability to manually specify when
last should be asserted (to handle replays).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
I join everyone and their mother in creating my own UART. 8n1 only, and 2
baud rates. Accepts AXI-stream.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a basic hub wrapper module which incorperates the core
introduced in b68e131 ("Add a basic hub"). For each port, it
instantiates a phy (itself using a phy_internal wrapper) and an elastic
buffer. A WISHBONE parameter is used to control whether to instantiate a
wishbone interface. When disabled, we just respond to any request with
err. I've ommitted a separate testbench for phy_internal, since it is
much easier to create a smoke test using the hub interface.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a simple wishbone mux. The idea is that each slave gets its
own address bit. This lends itself to extemely simple address decoding,
but uses up address space quickly. In theory, we could also give larger
addres space to some slaves, but currently lower bits have priority. The
testbench is also very simple. Since everything is combinatorial, we can
determine the outputs from the inputs exactly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This module will make it easier to observe internal signals which would
otherwise be too short to see, or would trigger too fast to distinguish.
Continuous triggered will cause blinking, so signals which are expected
to be high for a while (e.g. level-based and not edge-based) should not
use this module.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
In order to move data between MIIs without implementing a MAC, we need
some kind of elastic buffer to bring the data into the transmit "clock
(enable) domain." Implement one. It's based on a classic shift-register
FIFO, with the main difference being the MII interfaces and the
elasticity (achieved by delaying asserting RX_DV until we reach the
WATERMARK). We use a register-based buffer because we only need to deal
with an under-/over-flow of 5 or so clocks for a 2000-byte packet. The
per-stage resource increase works out to 6 FFs and 1 LUT, which is
pretty much optimal.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a basic clause 27 repeater (hub), mostly for test purposes.
It's effectively just the state machine in figure 27-4 and nothing else
(e.g. no partitioning or jabber detection). This is surprisingly simple.
Unfortunately, yosys doesn't allow memories in port declarations, even
for systemverilog. This complicates the implementation and testbench,
since we have to do the slicing ourselves. This is particularly awful
for the testbench, since
module.signal[0].value != module.signal.value[0]
and module.signal can't be indexed by slices, and module.signal.value is
big endian (ugh ugh ugh). There is no clean solution here.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds support for half-duplex. This is mostly done by predicating
col and crs on half_duplex. In one place we need to go to IPG_LATE
directly (although we could go to IPG_LATE like FCS with no loss of
standard compliance).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
get_sim_time can return floating point values. This will cause tests to
fail since there is an epsilon of error. Fix this by timing things in
steps (which is always an int).
Fixes: 0495ae3 ("Add TX MAC (most of it)")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We might not release rst synchronously if clk was already high. Fix this
by forcing clk to z.
Fixes: 19f2f65 ("axis_mii_tx: Add reset")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
If we ever see an error, we shouldn't retry if we get a collision at the
same time, as we will just have to jam next time. Test for this case
instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Allow delaying the last byte to make it easier to exactly time when the
MAC sees the byte. This way, we can test to ensure that everything works
even when valid is only high for one cycle. We can't change signals
once valid goes high, so this is the only way to ensure this kind of
timing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We don't need to delay after sending the last byte, and it makes it more
difficult to time subsequent packets correctly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds the transmit half of a MAC, supporting 100M and half-duplex.
It's roughly analogous to the axis_(x)gmii_tx modules in Alex
Forencich's ethernet repo. I've taken the approach of moving all state
into the state variable. All decisions are made once and have a
different state for each path. For example, instead of checking against
a "bytes_sent" variable to determine what to do on collision, we have a
different state for each set of actions.
This whole module is heinously complex, especially because of the many
corner cases caused by the spec. I have probably not tested it nearly
enough, but the basics of sending packets have mostly had the bugs wrung
out.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The downstream TX side of the MII is almost the same as the upstream RX
side of the MII. However, MACs may never generate TX_ER, so I will be
leaving it out. TO allow testing this, make the err signal optional.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Detecting non-clock signal edges with RisingEdge and FallingEdge is not
very robust, and is recommended against. Track edges manually.
Fixes: f6f3f02 ("Add phy_core")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson