axis_wb_bridge: Fix AXIS master
The AXI stream master doesn't cope with slaves that aren't ready all the
time. There are two separate issues: first, the data was only valid for one
cycle. Second, the handshake logic was incorrect. Rectify these, and modify
the testbench to test for this condition.
Fixes: 7514231
("Add AXIS-Wishbone bridge")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
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d2b4351899
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10a4199381
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@ -46,7 +46,7 @@ module axis_wb_bridge (
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localparam RESP1 = 9;
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localparam RESP0 = 10;
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reg s_axis_ready_next, s_axis_valid_last, m_axis_ready_last, m_axis_valid_next;
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reg s_axis_ready_next, s_axis_valid_last, m_axis_valid_next;
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reg [7:0] s_axis_data_last, m_axis_data_next;
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reg wb_ack_last, wb_err_last;
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reg wb_stb_next, wb_we_next;
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@ -58,7 +58,7 @@ module axis_wb_bridge (
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always @(*) begin
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s_axis_ready_next = s_axis_ready;
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m_axis_valid_next = m_axis_valid;
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m_axis_data_next = 8'bX;
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m_axis_data_next = m_axis_data;
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wb_cyc = wb_stb;
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wb_stb_next = wb_stb;
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@ -137,15 +137,15 @@ module axis_wb_bridge (
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overflow_latch_next = 0;
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state_next = wb_we || wb_err ? RESP0 : RESP2;
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end
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RESP2: if (m_axis_ready_last) begin
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RESP2: if (m_axis_ready && m_axis_valid) begin
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m_axis_data_next = wb_data_latch[15:8];
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state_next = RESP1;
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end
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RESP1: if (m_axis_ready_last) begin
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RESP1: if (m_axis_ready && m_axis_valid) begin
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m_axis_data_next = wb_data_latch[7:0];
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state_next = RESP0;
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end
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RESP0: if (m_axis_ready_last) begin
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RESP0: if (m_axis_ready && m_axis_valid) begin
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m_axis_valid_next = 0;
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s_axis_ready_next = 1;
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state_next = IDLE;
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@ -167,7 +167,6 @@ module axis_wb_bridge (
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if (rst) begin
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s_axis_ready <= 1;
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s_axis_valid_last <= 0;
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m_axis_ready_last <= 0;
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m_axis_valid <= 0;
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wb_ack_last <= 0;
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wb_err_last <= 0;
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@ -177,7 +176,6 @@ module axis_wb_bridge (
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end else begin
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s_axis_ready <= s_axis_ready_next;
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s_axis_valid_last <= s_axis_valid;
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m_axis_ready_last <= m_axis_ready;
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m_axis_valid <= m_axis_valid_next;
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wb_ack_last <= wb_ack;
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wb_err_last <= wb_err;
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@ -4,11 +4,12 @@
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import cocotb
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from cocotb.binary import BinaryValue
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from cocotb.clock import Clock
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from cocotb.regression import TestFactory
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from cocotb.triggers import FallingEdge, Timer
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from .axis_replay_buffer import send_packet, recv_packet
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from .mdio import wb_read, wb_write, wb_err
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from .util import BIT, GENMASK
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from .util import BIT, ClockEnable, GENMASK, timeout
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CMD_CLEAR = BIT(0)
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CMD_WE = BIT(1)
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@ -68,8 +69,8 @@ class Encoder:
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self.last_addr = (addr & ~GENMASK(7, 0)) | ((addr + postinc) & GENMASK(7, 0))
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return (cmd, *addr_bytes, *data_bytes)
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@cocotb.test(timeout_time=10, timeout_unit='us')
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async def test_bridge(bridge):
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@timeout(10, 'us')
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async def test_bridge(bridge, in_ratio, out_ratio):
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bridge.clk.value = BinaryValue('Z')
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bridge.rst.value = 1
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bridge.s_axis_valid.value = 0
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@ -82,6 +83,7 @@ async def test_bridge(bridge):
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bridge.rst.value = 0
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await cocotb.start(Clock(bridge.clk, 8, units='ns').start())
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await FallingEdge(bridge.clk)
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await cocotb.start(ClockEnable(bridge.clk, bridge.m_axis_ready, out_ratio))
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s_axis = {
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'clk': bridge.clk,
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@ -112,7 +114,7 @@ async def test_bridge(bridge):
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e = Encoder()
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async def read(addr, data, postinc=False, resp=0):
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await send_packet(s_axis, e.encode(addr, None, postinc))
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await send_packet(s_axis, e.encode(addr, None, postinc), in_ratio)
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bridge.overflow.value = bool(resp & STATUS_OVERFLOW)
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if resp & STATUS_ERR:
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@ -125,7 +127,7 @@ async def test_bridge(bridge):
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await recv_packet(m_axis, (resp, *data.to_bytes(2, 'big')))
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async def write(addr, data, postinc=False, resp=STATUS_WE):
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await send_packet(s_axis, e.encode(addr, data, postinc))
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await send_packet(s_axis, e.encode(addr, data, postinc), in_ratio)
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bridge.overflow.value = bool(resp & STATUS_OVERFLOW)
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if resp & STATUS_ERR:
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@ -164,3 +166,8 @@ async def test_bridge(bridge):
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await read(7, 8, resp=STATUS_ERR)
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await read(9, 10, resp=STATUS_OVERFLOW)
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await write(11, 12)
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bridge_tests = TestFactory(test_bridge)
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bridge_tests.add_option('in_ratio', (1, 4))
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bridge_tests.add_option('out_ratio', (1, 4))
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bridge_tests.generate_tests()
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