uart_tx: Add reset

Add a reset to match uart_rx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

rtl/uart_tx.v

@@ -8,7 +8,7 @@
 `include "common.vh"
 
 module uart_tx (
-	input clk,
+	input clk, rst,
 
 	input [7:0] data,
 	output reg ready,
@@ -31,12 +31,6 @@ module uart_tx (
 	reg [3:0] counter, counter_next;
 	reg [8:0] bits, bits_next;
 
-	initial begin
-		ready = 1'b1;
-		valid_last = 1'b0;
-		bits = 9'h1ff;
-	end	
-
 	always @(*) begin
 		tx = bits[0];
 
@@ -64,11 +58,21 @@ module uart_tx (
 
 	always @(posedge clk) begin
 		data_last <= data;
-		ready <= ready_next;
-		valid_last <= valid;
 		counter <= counter_next;
 		lfsr <= lfsr_next;
-		bits <= bits_next;
 	end
 
+	always @(posedge clk, posedge rst) begin
+		if (rst) begin
+			ready <= 1'b1;
+			valid_last <= 1'b0;
+			bits <= 9'h1ff;
+		end else begin
+			ready <= ready_next;
+			valid_last <= valid;
+			bits <= bits_next;
+		end
+	end
+
+
 endmodule

tb/uart_tx.py

@@ -15,10 +15,12 @@ BIT_STEPS = get_sim_steps(1 / BAUD, 'sec', round_mode='round')
 @cocotb.test(timeout_time=1, timeout_unit='ms')
 async def test_tx(uart):
     uart.clk.value = BinaryValue('Z')
+    uart.rst.value = 1
     uart.valid.value = 0
     uart.high_speed.value = BAUD == 4e6
 
     await Timer(1)
+    uart.rst.value = 0
     await cocotb.start(Clock(uart.clk, 8, units='ns').start())
     await FallingEdge(uart.clk)