Add MII elastic buffer
In order to move data between MIIs without implementing a MAC, we need some kind of elastic buffer to bring the data into the transmit "clock (enable) domain." Implement one. It's based on a classic shift-register FIFO, with the main difference being the MII interfaces and the elasticity (achieved by delaying asserting RX_DV until we reach the WATERMARK). We use a register-based buffer because we only need to deal with an under-/over-flow of 5 or so clocks for a 2000-byte packet. The per-stage resource increase works out to 6 FFs and 1 LUT, which is pretty much optimal. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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Sean Anderson
parent
5cf02e9490
commit
16b639aad2
1
Makefile
1
Makefile
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@ -116,6 +116,7 @@ MODULES += descramble
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MODULES += mdio
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MODULES += mdio_io
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MODULES += mdio_regs
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MODULES += mii_elastic_buffer
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MODULES += mii_io_rx
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MODULES += mii_io_tx
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MODULES += nrzi_decode
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@ -0,0 +1,145 @@
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// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*
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* This is a classic shift-register FIFO (a la XAPP 005.002) adapted for MII
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* semantics. The semantics of err/valid are slightly different from dv/er
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* when we have err and not valid. We remove this scenario from the input
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* (since it represents false carrier/LPI and we don't care about those when
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* repeating) and reuse this scenario as filler to indicate underflow.
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*
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* There is a delay of BUF_SIZE - 1 clocks between when data enters via txd
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* and when it is offered on rxd.
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*
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* Note that because this module reacts to rx_ce/rx_dv from the previous clock,
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* the maximum duty cycle of rx_ce is 50%. Otherwise, it is possible for the
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* same data to be offered more than once.
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*/
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`include "common.vh"
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module mii_elastic_buffer (
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input clk,
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input tx_ce,
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input tx_en,
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input tx_er,
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input [3:0] txd,
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input rx_ce,
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output reg rx_dv,
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output reg rx_er,
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output reg [3:0] rxd,
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output reg overflow,
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output reg underflow
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);
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parameter BUF_SIZE = 5;
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/*
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* The amount of data in the buffer before we assert RX_DV. The
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* default slightly favors overflow (tx_ce faster than rx_ce) over
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* underflow. This is because we can generally get more data through
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* with overflow, since the slower rx_ce allows the data in the buffer
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* to propegate more.
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*/
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parameter WATERMARK = (BUF_SIZE + 1) / 2;
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integer i;
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reg [BUF_SIZE - 1:0] valid, valid_next, err, err_next;
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reg [3:0] data [BUF_SIZE - 1:0], data_next [BUF_SIZE - 1:0];
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reg shift, overflow_next, underflow_next;
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reg in, in_next, out, out_next, rx_ce_last, rx_dv_last;
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reg [BUF_SIZE - 1:0] debug;
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initial begin
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valid = 0;
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err = 0;
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overflow = 0;
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underflow = 0;
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in = 0;
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out = 0;
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rx_dv_last = 0;
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rx_ce_last = 0;
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end
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always @(*) begin
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if (out)
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rx_dv = valid[BUF_SIZE - 1];
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else
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rx_dv = &valid[BUF_SIZE - 1:BUF_SIZE - WATERMARK - 1];
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rx_er = err[BUF_SIZE - 1];
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underflow_next = 0;
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if (err[BUF_SIZE - 1] && !valid[BUF_SIZE - 1]) begin
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rx_dv = 1;
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underflow_next = rx_ce;
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end
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rxd = data[BUF_SIZE - 1];
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out_next = rx_ce ? rx_dv : out;
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valid_next = valid;
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err_next = err;
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shift = rx_ce_last && rx_dv_last;
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debug[BUF_SIZE - 1] = shift;
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for (i = BUF_SIZE - 1; i > 0; i = i - 1) begin
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data_next[i] = data[i];
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if (shift || !valid[i]) begin
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valid_next[i] = valid[i - 1];
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err_next[i] = err[i - 1];
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data_next[i] = data[i - 1];
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shift = 1;
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end
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debug[i - 1] = shift;
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end
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data_next[0] = data[0];
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if (shift) begin
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valid_next[0] = 0;
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err_next[0] = in;
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data_next[0] = 4'hX;
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end
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overflow_next = 0;
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in_next = in;
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if (tx_ce) begin
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if (tx_en) begin
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valid_next[0] = 1;
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err_next[0] = tx_er;
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if (valid[0] && !shift) begin
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overflow_next = 1;
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err_next[0] = 1;
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end
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in_next = 1;
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end else begin
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valid_next[0] = 0;
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err_next[0] = 0;
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in_next = 0;
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end
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data_next[0] = txd;
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end
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end
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always @(posedge clk) begin
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valid <= valid_next;
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err <= err_next;
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for (i = 0; i < BUF_SIZE; i = i + 1)
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data[i] <= data_next[i];
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overflow <= overflow_next;
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underflow <= underflow_next;
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in <= in_next;
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out <= out_next;
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rx_ce_last <= rx_ce;
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rx_dv_last <= rx_dv;
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end
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`ifndef SYNTHESIS
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/* This is the only way to look into a buffer... */
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genvar j;
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generate for (j = 0; j < BUF_SIZE; j = j + 1) begin
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wire tmpv = valid[j];
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wire tmpe = err[j];
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wire [3:0] tmpd = data[j];
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end endgenerate
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`endif
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endmodule
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@ -0,0 +1,103 @@
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# SPDX-License-Identifier: AGPL-3.0-Only
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# Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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import cocotb
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from cocotb.binary import BinaryValue
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from cocotb.clock import Clock
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from cocotb.regression import TestFactory
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from cocotb.triggers import ClockCycles, FallingEdge, RisingEdge, Timer
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from .pcs_rx import mii_recv_packet
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from .pcs_tx import mii_send_packet
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from .util import alist, ClockEnable, lookahead, timeout
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@cocotb.test(timeout_time=50, timeout_unit='us')
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async def test_elastic(buf):
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buf.clk.value = BinaryValue('Z')
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buf.tx_ce.value = 0
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buf.tx_en.value = 0
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buf.rx_ce.value = 0
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await Timer(1)
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await cocotb.start(Clock(buf.clk, 8, units='ns').start())
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await FallingEdge(buf.clk)
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await cocotb.start(ClockEnable(buf.clk, buf.tx_ce, 5))
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await FallingEdge(buf.clk)
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rx_ce = await cocotb.start(ClockEnable(buf.clk, buf.rx_ce, 5))
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underflows = 0
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overflows = 0
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async def count_excursions():
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nonlocal underflows, overflows
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while True:
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await RisingEdge(buf.clk)
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underflows += buf.underflow.value
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overflows += buf.overflow.value
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await cocotb.start(count_excursions())
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in_signals = {
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'ce': buf.tx_ce,
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'enable': buf.tx_en,
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'err': buf.tx_er,
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'data': buf.txd,
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}
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out_signals = {
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'ce': buf.rx_ce,
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'err': buf.rx_er,
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'data': buf.rxd,
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'valid': buf.rx_dv,
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}
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for packet in (list(range(10)), [0, 1, 2, None, 4, 5]):
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await cocotb.start(mii_send_packet(buf, packet, in_signals))
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assert packet == await alist(mii_recv_packet(buf, out_signals))
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packet = list(range(10))
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for ratio in (2, 12):
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rx_ce.kill()
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while not buf.tx_ce.value:
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await RisingEdge(buf.clk)
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rx_ce = await cocotb.start(ClockEnable(buf.clk, buf.rx_ce, ratio))
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underflows = 0
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overflows = 0
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await cocotb.start(mii_send_packet(buf, packet, in_signals))
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outs = await alist(mii_recv_packet(buf, out_signals))
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if ratio > 5:
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assert overflows
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else:
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assert underflows
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last = None
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for nibble in outs:
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if nibble is not None:
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try:
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int(nibble)
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except:
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raise
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assert nibble != last
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last = nibble
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packet = list(range(5))
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for ratio in (4, 6):
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# Wait for a CE before shutting it off; we need to output at least one idle
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while not buf.rx_ce.value:
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await FallingEdge(buf.clk)
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await FallingEdge(buf.clk)
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rx_ce.kill()
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underflows = 0
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overflows = 0
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await cocotb.start(mii_send_packet(buf, packet, in_signals))
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# Set up a worst-case scenario
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while not buf.rx_dv.value:
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await FallingEdge(buf.clk)
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if ratio == 6:
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await ClockCycles(buf.clk, 5, False)
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rx_ce = await cocotb.start(ClockEnable(buf.clk, buf.rx_ce, ratio))
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# And make sure everything works out
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assert packet == await alist(mii_recv_packet(buf, out_signals))
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