tb: util: Use RisingEdge for ClockEnable

Signals modified by cocotb tasks may not be visible to other tasks on
the same clock cycle. This was causing issues for recv_packet, because
it might not see the same values for ready/valid driven by ClockEnable
that the DUT sees. This was worked around by sampling on the RisingEdge.
However, this can cause recv_packet to miss data. Fix this by using
RisingEdge for ClockEnable, so everything can be sampled on the
FallingEdge.

Fixes: 52325f2 ("Add AXI stream replay buffer")
Signed-off-by: Sean Anderson <seanga2@gmail.com>

tb/axis_replay_buffer.py

@@ -42,11 +42,11 @@ async def recv_packet(signals, packet, last=None):
 
     for i, val in enumerate(packet):
         while not signals['valid'].value or not signals['ready'].value:
-            await RisingEdge(signals['clk'])
+            await FallingEdge(signals['clk'])
         assert signals['data'].value == val
         if 'last' in signals:
             assert signals['last'].value == (i == last - 1)
-        await RisingEdge(signals['clk'])
+        await FallingEdge(signals['clk'])
 
 @timeout(30, 'us')
 async def test_replay(buf, in_ratio, out_ratio):

tb/util.py

@@ -150,9 +150,9 @@ async def ClockEnable(clk, ce, ratio):
         return
 
     while True:
-        await ClockCycles(clk, 1, False)
+        await ClockCycles(clk, 1)
         ce.value = 0
-        await ClockCycles(clk, ratio - 1, False)
+        await ClockCycles(clk, ratio - 1)
         ce.value = 1
 
 # Adapted from https://stackoverflow.com/a/1630350/5086505