axis_mii_tx: Add reset
Yosys doesn't optimize FSMs without resets. Add one so ours gets optimized. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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Sean Anderson
parent
23913a6b77
commit
19f2f656cd
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@ -18,7 +18,7 @@
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*/
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module axis_mii_tx (
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input clk,
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input clk, rst,
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/* MII */
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output reg mii_tx_ce,
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@ -155,17 +155,13 @@ module axis_mii_tx (
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wire [7:0] buf_data;
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wire buf_err, buf_valid, buf_last;
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reg buf_ready, buf_ready_next, replay, replay_next, done, done_next;
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initial begin
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buf_ready = 0;
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done = 0;
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replay = 0;
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end
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axis_replay_buffer #(
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.DATA_WIDTH(9),
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.BUF_SIZE(DATA_EARLY_BYTES)
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) replay_buffer (
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.clk(clk),
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.rst(rst),
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.s_axis_data({ axis_data, axis_err }),
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.s_axis_valid(axis_valid),
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.s_axis_ready(axis_ready),
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@ -188,24 +184,6 @@ module axis_mii_tx (
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reg transmit_ok_next, gave_up_next, late_collision_next;
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reg underflow_next;
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initial begin
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mii_tx_counter = MII_100_RATIO;
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mii_tx_ce = 0;
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mii_tx_ce_next = 0;
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mii_tx_ce_next_next = 0;
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mii_tx_en = 0;
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mii_txd = 0;
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odd = 0;
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state = IPG_EARLY;
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state_counter = IPG_EARLY_BYTES - 1;
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retries = MAX_RETRIES - 1;
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lfsr = 10'h3ff;
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transmit_ok = 0;
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gave_up = 0;
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late_collision = 0;
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underflow = 0;
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end
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always @(*) begin
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mii_tx_ce_next_next_next = 0;
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mii_tx_counter_next = mii_tx_counter - 1;
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@ -503,30 +481,51 @@ module axis_mii_tx (
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endcase
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end
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always @(posedge clk) begin
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mii_tx_ce <= mii_tx_ce_next;
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mii_tx_ce_next <= mii_tx_ce_next_next;
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mii_tx_ce_next_next <= mii_tx_ce_next_next_next;
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mii_tx_counter <= mii_tx_counter_next;
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mii_tx_en <= mii_tx_en_next;
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mii_txd <= odd_next ? data_next[7:4] : data_next[3:0];
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do_crc <= do_crc_next;
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odd <= odd_next;
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state <= state_next;
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state_counter <= state_counter_next;
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buf_ready <= buf_ready_next;
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data <= data_next;
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replay <= replay_next;
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done <= done_next;
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retries <= retries_next;
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backoff <= backoff_next;
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lfsr <= lfsr_next;
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crc_state <= crc_state_next;
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collision <= collision_next;
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transmit_ok <= transmit_ok_next;
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gave_up <= gave_up_next;
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late_collision <= late_collision_next;
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underflow <= underflow_next;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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mii_tx_counter <= MII_100_RATIO;
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mii_tx_ce <= 0;
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mii_tx_ce_next <= 0;
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mii_tx_ce_next_next <= 0;
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mii_tx_en <= 0;
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mii_txd <= 0;
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odd <= 0;
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state <= IPG_EARLY;
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state_counter <= IPG_EARLY_BYTES - 1;
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retries <= MAX_RETRIES - 1;
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lfsr <= 10'h3ff;
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transmit_ok <= 0;
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gave_up <= 0;
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late_collision <= 0;
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underflow <= 0;
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buf_ready <= 0;
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done <= 0;
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replay <= 0;
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end else begin
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mii_tx_ce <= mii_tx_ce_next;
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mii_tx_ce_next <= mii_tx_ce_next_next;
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mii_tx_ce_next_next <= mii_tx_ce_next_next_next;
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mii_tx_counter <= mii_tx_counter_next;
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mii_tx_en <= mii_tx_en_next;
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mii_txd <= odd_next ? data_next[7:4] : data_next[3:0];
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do_crc <= do_crc_next;
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odd <= odd_next;
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state <= state_next;
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state_counter <= state_counter_next;
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buf_ready <= buf_ready_next;
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data <= data_next;
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replay <= replay_next;
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done <= done_next;
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retries <= retries_next;
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backoff <= backoff_next;
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lfsr <= lfsr_next;
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crc_state <= crc_state_next;
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collision <= collision_next;
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transmit_ok <= transmit_ok_next;
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gave_up <= gave_up_next;
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late_collision <= late_collision_next;
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underflow <= underflow_next;
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end
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end
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`ifndef SYNTHESIS
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@ -25,7 +25,7 @@
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`include "common.vh"
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module axis_replay_buffer (
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input clk,
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input clk, rst,
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/* AXI Stream slave */
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input [DATA_WIDTH - 1:0] s_axis_data,
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@ -72,19 +72,6 @@ module axis_replay_buffer (
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reg last, last_next;
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reg full, full_next, empty, replayable_next, we, re;
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initial begin
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m_ptr = 0;
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s_ptr = 0;
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last = 0;
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replayable = 1;
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s_axis_valid_last = 0;
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s_axis_last_last = 0;
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s_axis_ready = 1;
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m_axis_valid = 0;
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m_axis_last = 0;
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sent_last = 0;
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end
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always @(*) begin
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we = 0;
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s_ptr_next = s_ptr;
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@ -157,19 +144,34 @@ module axis_replay_buffer (
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buffer[s_ptr[BUF_WIDTH - 1:0]] <= { s_axis_data_last };
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if (re)
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{ m_axis_data } <= buffer[m_ptr[BUF_WIDTH - 1:0]];
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end
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s_axis_data_last <= s_axis_data;
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s_axis_valid_last <= s_axis_valid;
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s_axis_last_last <= s_axis_last;
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s_axis_ready <= s_axis_ready_next;
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m_axis_last <= m_axis_last_next;
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m_axis_valid <= m_axis_valid_next;
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sent_last <= sent_last_next;
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m_ptr <= m_ptr_next;
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s_ptr <= s_ptr_next;
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last <= last_next;
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last_ptr <= last_ptr_next;
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replayable <= replayable_next;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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m_ptr <= 0;
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s_ptr <= 0;
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last <= 0;
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replayable <= 1;
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s_axis_valid_last <= 0;
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s_axis_last_last <= 0;
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s_axis_ready <= 1;
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m_axis_valid <= 0;
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m_axis_last <= 0;
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sent_last <= 0;
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end else begin
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s_axis_data_last <= s_axis_data;
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s_axis_valid_last <= s_axis_valid;
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s_axis_last_last <= s_axis_last;
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s_axis_ready <= s_axis_ready_next;
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m_axis_last <= m_axis_last_next;
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m_axis_valid <= m_axis_valid_next;
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sent_last <= sent_last_next;
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m_ptr <= m_ptr_next;
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s_ptr <= s_ptr_next;
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last <= last_next;
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last_ptr <= last_ptr_next;
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replayable <= replayable_next;
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end
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end
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`ifndef SYNTHESIS
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@ -21,13 +21,16 @@ import os
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skip_slow = not os.environ.get('RUN_SLOW', False)
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async def init(mac):
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mac.rst.value = 1
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mac.mii_col.value = 0
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mac.mii_crs.value = 0
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mac.axis_valid.value = 0
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mac.axis_err.value = 0
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mac.short_backoff.value = 1
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await Timer(1)
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mac.rst.value = 0
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await cocotb.start(Clock(mac.clk, 8, units='ns').start())
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await FallingEdge(mac.clk)
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def send_packet(mac, packet, ratio=1):
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return axis_replay_buffer.send_packet({
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@ -34,6 +34,7 @@ async def send_packet(signals, packet, ratio=1):
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@timeout(30, 'us')
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async def test_replay(buf, in_ratio, out_ratio):
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buf.rst.value = 1
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buf.s_axis_valid.value = 0
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buf.s_axis_last.value = 0
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buf.m_axis_ready.value = 1
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@ -41,6 +42,7 @@ async def test_replay(buf, in_ratio, out_ratio):
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buf.done.value = 0
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await Timer(1)
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buf.rst.value = 0
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await cocotb.start(Clock(buf.clk, 8, units='ns').start())
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await FallingEdge(buf.clk)
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await cocotb.start(ClockEnable(buf.clk, buf.m_axis_ready, out_ratio))
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