From 19f2f656cd3b81f23b0bf3f7fb8a24c0bec37872 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 10 Jan 2023 23:52:46 -0500 Subject: [PATCH] axis_mii_tx: Add reset Yosys doesn't optimize FSMs without resets. Add one so ours gets optimized. Signed-off-by: Sean Anderson --- rtl/axis_mii_tx.v | 95 ++++++++++++++++++++-------------------- rtl/axis_replay_buffer.v | 54 ++++++++++++----------- tb/axis_mii_tx.py | 3 ++ tb/axis_replay_buffer.py | 2 + 4 files changed, 80 insertions(+), 74 deletions(-) diff --git a/rtl/axis_mii_tx.v b/rtl/axis_mii_tx.v index da337d8..2873d01 100644 --- a/rtl/axis_mii_tx.v +++ b/rtl/axis_mii_tx.v @@ -18,7 +18,7 @@ */ module axis_mii_tx ( - input clk, + input clk, rst, /* MII */ output reg mii_tx_ce, @@ -155,17 +155,13 @@ module axis_mii_tx ( wire [7:0] buf_data; wire buf_err, buf_valid, buf_last; reg buf_ready, buf_ready_next, replay, replay_next, done, done_next; - initial begin - buf_ready = 0; - done = 0; - replay = 0; - end axis_replay_buffer #( .DATA_WIDTH(9), .BUF_SIZE(DATA_EARLY_BYTES) ) replay_buffer ( .clk(clk), + .rst(rst), .s_axis_data({ axis_data, axis_err }), .s_axis_valid(axis_valid), .s_axis_ready(axis_ready), @@ -188,24 +184,6 @@ module axis_mii_tx ( reg transmit_ok_next, gave_up_next, late_collision_next; reg underflow_next; - initial begin - mii_tx_counter = MII_100_RATIO; - mii_tx_ce = 0; - mii_tx_ce_next = 0; - mii_tx_ce_next_next = 0; - mii_tx_en = 0; - mii_txd = 0; - odd = 0; - state = IPG_EARLY; - state_counter = IPG_EARLY_BYTES - 1; - retries = MAX_RETRIES - 1; - lfsr = 10'h3ff; - transmit_ok = 0; - gave_up = 0; - late_collision = 0; - underflow = 0; - end - always @(*) begin mii_tx_ce_next_next_next = 0; mii_tx_counter_next = mii_tx_counter - 1; @@ -503,30 +481,51 @@ module axis_mii_tx ( endcase end - always @(posedge clk) begin - mii_tx_ce <= mii_tx_ce_next; - mii_tx_ce_next <= mii_tx_ce_next_next; - mii_tx_ce_next_next <= mii_tx_ce_next_next_next; - mii_tx_counter <= mii_tx_counter_next; - mii_tx_en <= mii_tx_en_next; - mii_txd <= odd_next ? data_next[7:4] : data_next[3:0]; - do_crc <= do_crc_next; - odd <= odd_next; - state <= state_next; - state_counter <= state_counter_next; - buf_ready <= buf_ready_next; - data <= data_next; - replay <= replay_next; - done <= done_next; - retries <= retries_next; - backoff <= backoff_next; - lfsr <= lfsr_next; - crc_state <= crc_state_next; - collision <= collision_next; - transmit_ok <= transmit_ok_next; - gave_up <= gave_up_next; - late_collision <= late_collision_next; - underflow <= underflow_next; + always @(posedge clk, posedge rst) begin + if (rst) begin + mii_tx_counter <= MII_100_RATIO; + mii_tx_ce <= 0; + mii_tx_ce_next <= 0; + mii_tx_ce_next_next <= 0; + mii_tx_en <= 0; + mii_txd <= 0; + odd <= 0; + state <= IPG_EARLY; + state_counter <= IPG_EARLY_BYTES - 1; + retries <= MAX_RETRIES - 1; + lfsr <= 10'h3ff; + transmit_ok <= 0; + gave_up <= 0; + late_collision <= 0; + underflow <= 0; + buf_ready <= 0; + done <= 0; + replay <= 0; + end else begin + mii_tx_ce <= mii_tx_ce_next; + mii_tx_ce_next <= mii_tx_ce_next_next; + mii_tx_ce_next_next <= mii_tx_ce_next_next_next; + mii_tx_counter <= mii_tx_counter_next; + mii_tx_en <= mii_tx_en_next; + mii_txd <= odd_next ? data_next[7:4] : data_next[3:0]; + do_crc <= do_crc_next; + odd <= odd_next; + state <= state_next; + state_counter <= state_counter_next; + buf_ready <= buf_ready_next; + data <= data_next; + replay <= replay_next; + done <= done_next; + retries <= retries_next; + backoff <= backoff_next; + lfsr <= lfsr_next; + crc_state <= crc_state_next; + collision <= collision_next; + transmit_ok <= transmit_ok_next; + gave_up <= gave_up_next; + late_collision <= late_collision_next; + underflow <= underflow_next; + end end `ifndef SYNTHESIS diff --git a/rtl/axis_replay_buffer.v b/rtl/axis_replay_buffer.v index 1f305fb..00fb856 100644 --- a/rtl/axis_replay_buffer.v +++ b/rtl/axis_replay_buffer.v @@ -25,7 +25,7 @@ `include "common.vh" module axis_replay_buffer ( - input clk, + input clk, rst, /* AXI Stream slave */ input [DATA_WIDTH - 1:0] s_axis_data, @@ -72,19 +72,6 @@ module axis_replay_buffer ( reg last, last_next; reg full, full_next, empty, replayable_next, we, re; - initial begin - m_ptr = 0; - s_ptr = 0; - last = 0; - replayable = 1; - s_axis_valid_last = 0; - s_axis_last_last = 0; - s_axis_ready = 1; - m_axis_valid = 0; - m_axis_last = 0; - sent_last = 0; - end - always @(*) begin we = 0; s_ptr_next = s_ptr; @@ -157,19 +144,34 @@ module axis_replay_buffer ( buffer[s_ptr[BUF_WIDTH - 1:0]] <= { s_axis_data_last }; if (re) { m_axis_data } <= buffer[m_ptr[BUF_WIDTH - 1:0]]; + end - s_axis_data_last <= s_axis_data; - s_axis_valid_last <= s_axis_valid; - s_axis_last_last <= s_axis_last; - s_axis_ready <= s_axis_ready_next; - m_axis_last <= m_axis_last_next; - m_axis_valid <= m_axis_valid_next; - sent_last <= sent_last_next; - m_ptr <= m_ptr_next; - s_ptr <= s_ptr_next; - last <= last_next; - last_ptr <= last_ptr_next; - replayable <= replayable_next; + always @(posedge clk, posedge rst) begin + if (rst) begin + m_ptr <= 0; + s_ptr <= 0; + last <= 0; + replayable <= 1; + s_axis_valid_last <= 0; + s_axis_last_last <= 0; + s_axis_ready <= 1; + m_axis_valid <= 0; + m_axis_last <= 0; + sent_last <= 0; + end else begin + s_axis_data_last <= s_axis_data; + s_axis_valid_last <= s_axis_valid; + s_axis_last_last <= s_axis_last; + s_axis_ready <= s_axis_ready_next; + m_axis_last <= m_axis_last_next; + m_axis_valid <= m_axis_valid_next; + sent_last <= sent_last_next; + m_ptr <= m_ptr_next; + s_ptr <= s_ptr_next; + last <= last_next; + last_ptr <= last_ptr_next; + replayable <= replayable_next; + end end `ifndef SYNTHESIS diff --git a/tb/axis_mii_tx.py b/tb/axis_mii_tx.py index d9865ba..e31c408 100644 --- a/tb/axis_mii_tx.py +++ b/tb/axis_mii_tx.py @@ -21,13 +21,16 @@ import os skip_slow = not os.environ.get('RUN_SLOW', False) async def init(mac): + mac.rst.value = 1 mac.mii_col.value = 0 mac.mii_crs.value = 0 mac.axis_valid.value = 0 mac.axis_err.value = 0 mac.short_backoff.value = 1 await Timer(1) + mac.rst.value = 0 await cocotb.start(Clock(mac.clk, 8, units='ns').start()) + await FallingEdge(mac.clk) def send_packet(mac, packet, ratio=1): return axis_replay_buffer.send_packet({ diff --git a/tb/axis_replay_buffer.py b/tb/axis_replay_buffer.py index 7002e9e..de8d182 100644 --- a/tb/axis_replay_buffer.py +++ b/tb/axis_replay_buffer.py @@ -34,6 +34,7 @@ async def send_packet(signals, packet, ratio=1): @timeout(30, 'us') async def test_replay(buf, in_ratio, out_ratio): + buf.rst.value = 1 buf.s_axis_valid.value = 0 buf.s_axis_last.value = 0 buf.m_axis_ready.value = 1 @@ -41,6 +42,7 @@ async def test_replay(buf, in_ratio, out_ratio): buf.done.value = 0 await Timer(1) + buf.rst.value = 0 await cocotb.start(Clock(buf.clk, 8, units='ns').start()) await FallingEdge(buf.clk) await cocotb.start(ClockEnable(buf.clk, buf.m_axis_ready, out_ratio))