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11026 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 62d41d4639 opt_clean: Make the init attribute follow the FF's Q. 
Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
 2021-08-22 15:38:29 +02:00
github-actions[bot] 21e710eb55 Bump version 2021-08-21 00:48:23 +00:00
Pepijn de Vos c2d358484f
Gowin: deal with active-low tristate (#2971) 
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
 2021-08-20 21:21:06 +02:00
Miodrag Milanović c2866780d2
Merge pull request #2973 from YosysHQ/micko/optional_extensions 
Make Verific extensions optional
 2021-08-20 16:09:55 +02:00
Miodrag Milanovic b59c427348 Make Verific extensions optional 2021-08-20 10:19:04 +02:00
github-actions[bot] 75a4cdfc8a Bump version 2021-08-18 00:51:20 +00:00
Sylvain Munaut 3806b07303 ice40: Fix typo in SB_CARRY specify for LP/UltraPlus 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-17 14:33:30 +02:00
github-actions[bot] e6dd4db0af Bump version 2021-08-17 00:49:33 +00:00
Marcelina Kościelnicka 10f8b75dca kernel/mem: Remove old parameter when upgrading $mem to $mem_v2. 
Fixes #2967.
 2021-08-16 13:31:27 +02:00
github-actions[bot] 83c0f82dc8 Bump version 2021-08-15 00:50:04 +00:00
Marcelina Kościelnicka faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 
Fixes #2962.
 2021-08-14 15:26:11 +02:00
github-actions[bot] 539d4ee907 Bump version 2021-08-14 00:46:42 +00:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs 
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
 2021-08-13 17:11:35 -06:00
Marcelina Kościelnicka f791328506 Add opt_mem_widen pass. 
If all of us are wide, then none of us are!
 2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka 1f74ec3535 memory_share: Add -nosat and -nowiden options. 
This unlocks wide port recognition by default.
 2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka 9fdedf4d1c memory_dff: Recognize soft transparency logic. 2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka 616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00
Miodrag Milanović 30927df881
Merge pull request #2932 from YosysHQ/mwk/logger-check-expected 
logger: Add -check-expected subcommand.
 2021-08-13 11:45:20 +02:00
Brett Witherspoon 979053855c sv: improve support for wire and var with user-defined types 
- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
 2021-08-12 22:41:41 -06:00
github-actions[bot] c8023e37d8 Bump version 2021-08-13 00:50:48 +00:00
Marcelina Kościelnicka d0d9aca2c3 memory_share: Pass addresses through sigmap_xmux everywhere. 
This fixes wide port recognition in some cases.
 2021-08-13 01:17:55 +02:00
Marcelina Kościelnicka c58ac63c97 logger: Add -check-expected subcommand. 
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
 2021-08-12 17:41:39 +02:00
github-actions[bot] bfcd08a323 Bump version 2021-08-12 00:49:51 +00:00
Marcelina Kościelnicka b98376884e test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. 
These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations.  Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded.  Fix it with -deref and manual hierarchy call.

Shaves 30s off the test time on my machine.
 2021-08-11 14:52:38 +02:00
Marcelina Kościelnicka 72d86c327e memory_dff: Recognize read ports with reset / initial value. 2021-08-11 14:17:48 +02:00
Marcelina Kościelnicka 24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
github-actions[bot] b96eb888cc Bump version 2021-08-11 00:52:20 +00:00
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Michael Singer 681a1c07e5 Allow optional comma after last entry in enum 2021-08-09 22:25:57 -06:00
github-actions[bot] f368e2c7e6 Bump version 2021-08-10 00:52:49 +00:00
Marcelina Kościelnicka d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. 
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
 2021-08-09 16:54:35 +02:00
github-actions[bot] d8fcf1ab25 Bump version 2021-08-08 00:50:48 +00:00
Marcelina Kościelnicka 98003430d6 opt_merge: Use FfInitVals. 
Partial #2920 fix.
 2021-08-08 01:19:22 +02:00
github-actions[bot] a24906a7d2 Bump version 2021-08-07 00:45:55 +00:00
Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types. 
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
 2021-08-06 21:35:43 +02:00
github-actions[bot] 2e421feb0e Bump version 2021-08-05 00:51:08 +00:00
Marcelina Kościelnicka 63f9e0544f memory_share: Don't skip ports with EN wired to input for SAT sharing. 
Fixes #2912.
 2021-08-04 04:47:43 +02:00
github-actions[bot] d8b0c3277f Bump version 2021-08-04 00:49:53 +00:00
Marcelina Kościelnicka 8733e1923a memory_bram: Move init data swizzling before other swizzling. 
Fixes #2907.
 2021-08-03 15:04:10 +02:00
github-actions[bot] ca8ad62696 Bump version 2021-08-03 00:55:22 +00:00
Miodrag Milanovic be04d8834e Require latest verific 2021-08-02 10:29:58 +02:00
github-actions[bot] 10bcc4e192 Bump version 2021-08-02 00:50:24 +00:00
Marcelina Kościelnicka ec2a468bd3 backend/verilog: Add alternate mode for transparent read port output. 
This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
 2021-08-01 19:11:29 +02:00
Marcelina Kościelnicka 4451f7f5e9 memory_bram: Some refactoring 
This will make more sense when the new transparency masks land.

Fixes #2902.
 2021-08-01 16:51:24 +02:00
github-actions[bot] 12db9b4273 Bump version 2021-07-31 00:50:30 +00:00
Miodrag Milanović c4a295cb8d
Update version.yml 2021-07-30 19:50:02 +02:00
Maciej Dudek cfddef5d7d Fixes xc7 BRAM36s 
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-30 16:17:22 +02:00
Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards 
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
 2021-07-29 20:55:59 -04:00
Zachary Snow 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00