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6547 Commits

Author SHA1 Message Date
Clifford Wolf c6d8692c97 Add "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-20 15:06:28 +02:00
Eddie Hung 09beeee38a Try and fix again 2019-07-19 14:40:57 -07:00
Eddie Hung c926eeb43a Add another test 2019-07-19 14:02:46 -07:00
Eddie Hung cb0fd05215 Do not access beyond bounds 2019-07-19 13:58:50 -07:00
Eddie Hung 54708dfbd7 Add an SigSpec::at(offset, defval) convenience method 2019-07-19 13:54:57 -07:00
Eddie Hung 3a87dc3524 Wrap A and B in sigmap 2019-07-19 13:23:07 -07:00
Eddie Hung 31b0002e8c Remove "top" from message 2019-07-19 13:20:45 -07:00
Eddie Hung bcd8027182 Also optimise MSB of $sub 2019-07-19 13:11:48 -07:00
Eddie Hung 5bd088a686 Add one more test with trimming Y_WIDTH of $sub 2019-07-19 13:11:30 -07:00
Eddie Hung 415a2716df Be more explicit 2019-07-19 12:53:18 -07:00
Eddie Hung fc0e36d1c0 wreduce for $sub 2019-07-19 12:50:21 -07:00
Eddie Hung 4e9b1d36fa Add tests for sub too 2019-07-19 12:50:11 -07:00
Eddie Hung 3839bd50f2 Add test 2019-07-19 12:43:02 -07:00
Eddie Hung 25ff27e37f SigSpec::extract to take negative lengths 2019-07-19 12:34:04 -07:00
David Shah 80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah 79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
David Shah 3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung 171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
David Shah 9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft 0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
David Shah 8e0f7c18f1
Merge pull request #1207 from ZirconiumX/intel_new_pass_names 
synth_intel: rename for consistency with #1184
 2019-07-18 17:34:55 +01:00
Dan Ravensloft 50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Dan Ravensloft d5b3b3bc6f synth_intel: revert change to run_max10 2019-07-18 17:09:15 +01:00
Ben Widawsky 999811572a intel_synth: Fix help message 
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:25 +01:00
Ben Widawsky f950a7a75d intel_synth: Small code cleanup to remove if ladder 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:12 +01:00
Ben Widawsky 809b94a67b intel_synth: Make family explicit and match 
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:03 +01:00
Ben Widawsky 060e77c09b intel_synth: Minor code cleanups 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:05:54 +01:00
Dan Ravensloft c78ab8ebc5 synth_intel: rename for consistency with #1184 
Also fix a typo in the help message.
 2019-07-18 16:46:21 +01:00
Clifford Wolf e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels 
synth_{ice40,ecp5}: more sensible pass label naming
 2019-07-18 15:34:28 +02:00
Clifford Wolf 927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values 
write_verilog: dump zero width constants correctly
 2019-07-18 15:31:27 +02:00
Clifford Wolf 56c00e871f Remove old $pmux_safe code from write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-17 11:49:04 +02:00
David Shah 82153059a1
Merge pull request #1204 from smunaut/fix_1187 
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
 2019-07-17 07:55:26 +01:00
Sylvain Munaut f28e38de99 ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-07-16 23:57:15 +02:00
whitequark 4ff44d85a5 write_verilog: dump zero width constants correctly. 
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).
 2019-07-16 21:00:09 +00:00
Eddie Hung f8e470c1d1
Merge pull request #1202 from YosysHQ/cmp2lut_lut6 
cmp2lut transformation to support >32 bit LUT masks
 2019-07-16 13:52:43 -07:00
whitequark 698ab9beee synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
whitequark ba099bfe9b synth_{ice40,ecp5}: more sensible pass label naming. 2019-07-16 20:41:51 +00:00
Eddie Hung 7a58ee78dc gen_lut to return correctly sized LUT mask 2019-07-16 12:45:29 -07:00
Eddie Hung 8a2a2cd035 Forgot to commit 2019-07-16 12:44:26 -07:00
Eddie Hung dd10d2b00d Add tests for cmp2lut on LUT6 2019-07-16 12:11:59 -07:00
Eddie Hung 5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters 
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
 2019-07-16 08:53:47 -07:00
Eddie Hung ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix 
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
 2019-07-16 08:52:14 -07:00
Clifford Wolf a1a04ea79c
Merge pull request #1200 from mmicko/fix_typo_liberty_cc 
Fix typo, double "of"
 2019-07-16 15:27:25 +02:00
Clifford Wolf 928f0a4438
Merge pull request #1199 from mmicko/extract_fa_fix 
Fix check logic in extract_fa
 2019-07-16 15:27:09 +02:00
Miodrag Milanovic 6cce679b35 Fix typo, double "of" 2019-07-16 11:03:30 +02:00
Miodrag Milanovic 2b469e82a7 Fix check logic in extract_fa 2019-07-16 10:35:18 +02:00
Eddie Hung 87db41a2bb
Merge pull request #1196 from YosysHQ/eddie/fix1178 
Fix different synth results between with and without debug output "-g"
 2019-07-15 13:31:08 -07:00
Eddie Hung 5fb27c071b $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
Clifford Wolf 2a7198db51
Merge pull request #1189 from YosysHQ/eddie/fix1151 
Error out if enable > dbits in memory_bram file
 2019-07-15 20:06:35 +02:00