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10062 Commits

Author SHA1 Message Date
Eddie Hung da7da44919 abc9_ops: -reintegrate to be sensitive to start_offset too 2020-05-02 11:19:04 -07:00
Eddie Hung 2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Eddie Hung a0afa1787e aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf c3e5a070ea Add plusargs for output files in test_autotb output 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf f38d76efbf Bugfix in partsel.v signed indices test cases 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf 88185f8959 Fix handling of signed indices in bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf 749c2ff84a Add tests based on the test case from #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf 589ed2d970 Add AST_SELFSZ and improve handling of bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt 
Fix "opt_expr -fine" bug introduced in 213a89558
 2020-05-02 11:20:02 +02:00
whitequark ff7a8d0e1e Update ABC to include WASI support fixes. 2020-05-02 00:18:33 +00:00
whitequark b36060cc20 Fix WASI builds with abc enabled. 
This PR works around #2011.
 2020-05-01 23:57:35 +00:00
whitequark bbde241942
Merge pull request #2001 from whitequark/wasi 
Add WASI platform support
 2020-05-01 21:28:20 +00:00
Eddie Hung 7f9ecddb7f Add testcase for #2010 2020-05-01 14:07:33 -07:00
Claire Wolf 8ee32adac3 Fix "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-01 20:12:16 +02:00
Claire Wolf 667f38fe53
Merge pull request #1997 from whitequark/document-ootb 
Explain how to do out-of-tree builds in README
 2020-05-01 15:35:33 +02:00
Claire Wolf d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837 
Clear current_scope when done with RTLIL generation
 2020-05-01 14:58:41 +02:00
Alberto Gonzalez b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`. 2020-05-01 07:17:27 +00:00
whitequark b43c282e4e Add WASI platform support. 
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
 2020-04-30 18:56:25 +00:00
Eddie Hung bc380b0b56
Merge pull request #1999 from YosysHQ/eddie/verific_enum_again 
verific: recover wiretype/enum attr as part of import_attributes()
 2020-04-30 09:07:02 -07:00
whitequark 33c9c04561
Merge pull request #2008 from whitequark/editorconfig-abc 
Fix .editorconfig to not break abc
 2020-04-30 15:53:27 +00:00
Eddie Hung 5017ff4a97 verific: ignore anonymous enums 2020-04-30 07:48:47 -07:00
whitequark adeed6f730 Fix .editorconfig to not break abc. 2020-04-30 02:22:37 +00:00
Eddie Hung 97bfe65d3a verific: support VHDL enums too 2020-04-27 15:17:13 -07:00
Eddie Hung a66200ed1d
Merge pull request #1946 from YosysHQ/eddie/yosyshq_abc 
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
 2020-04-27 13:48:50 -07:00
Eddie Hung c34d57de2e Update CHANGELOG and manual for departure from upstream 2020-04-27 12:08:45 -07:00
Eddie Hung a3fa9fd6e9 abc: use YosysHQ/abc instead of upstream berkeley-abc/abc 
Enabling modifications
 2020-04-27 12:03:40 -07:00
Eddie Hung eabc00de8b
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help 
bugpoint: improve help text
 2020-04-27 11:12:17 -07:00
Vamsi K Vytla adb483ddfd frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire 2020-04-27 10:36:18 -07:00
Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL 
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
 2020-04-27 09:44:24 -07:00
Eddie Hung dd5f206d9e verific: recover wiretype/enum attr as part of import_attributes() 2020-04-27 08:43:54 -07:00
whitequark 868b6b1b0d
Merge pull request #2002 from YosysHQ/dave/cxxrtl-width 
cxxrtl: Round up constant width
 2020-04-25 18:30:53 +00:00
David Shah 1b93dda037 cxxrtl: Round up constant width 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-25 10:42:21 +01:00
whitequark 9b26a1fa89 README: explain how to do out-of-tree builds. 2020-04-24 23:27:43 +00:00
whitequark f1087b2552 Fix out-of-tree builds configured as `SMALL := 1`. 2020-04-24 23:27:43 +00:00
whitequark 26cda3c247 gowin,ecp5: remove generated files in `make clean`. 2020-04-24 23:26:39 +00:00
whitequark bbf343589b
Merge pull request #1998 from whitequark/cxxrtl-fixes 
cxxrtl: fix attribute syntax, minor fixes
 2020-04-24 22:44:35 +00:00
Eddie Hung 7f203cb019 tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
Eddie Hung b5f38f8342 opt_expr: const_xnor replacement to pad Y with 1'b1 2020-04-24 14:13:45 -07:00
Eddie Hung 56dd036b97 bugpoint: improve messaging 2020-04-24 13:41:19 -07:00
Eddie Hung e602184856 bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells 2020-04-24 13:26:04 -07:00
Eddie Hung b52eccef3a Revert "verific: import enum attributes from verific" 
This reverts commit 5028e17f7d.
 2020-04-24 11:57:55 -07:00
whitequark a0e658d412 cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.` 
The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
 2020-04-24 18:35:53 +00:00
Eddie Hung 4bfe6ebea9 bugpoint: skip ports with (* keep *) on; add header 2020-04-24 11:17:09 -07:00
Eddie Hung ebd6fa945d tests: opt_expr update xnor/xor tests 2020-04-24 11:16:25 -07:00
Eddie Hung 83570bc0da opt_expr: more fixes for $xor/$xnor 2020-04-24 11:15:29 -07:00
Claire Wolf 3eb24809a1
Merge pull request #1995 from YosysHQ/eddie/fix_verific_wiretype 
verific: do not assert if wire not found; warn instead
 2020-04-24 14:09:47 +02:00
Dan Ravensloft 4ca5f9799b intel_alm: cleanup duplication 2020-04-24 11:26:48 +02:00
whitequark f88378ae61 cxxrtl: improve printing of narrow memories. 2020-04-24 05:50:36 +00:00
whitequark 3738391bdd cxxrtl: fix handling of parametric modules with large parameters. 
These have a `$paramod$` prefix, not `$paramod\\`.
 2020-04-24 05:44:39 +00:00