mirror of https://github.com/YosysHQ/yosys.git
Fix out-of-tree builds configured as `SMALL := 1`.
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parent
26cda3c247
commit
f1087b2552
22
Makefile
22
Makefile
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@ -42,7 +42,7 @@ SANITIZER =
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# SANITIZER = undefined
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# SANITIZER = cfi
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PROGRAM_PREFIX :=
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PROGRAM_PREFIX :=
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OS := $(shell uname -s)
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PREFIX ?= /usr/local
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@ -584,10 +584,10 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc
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else
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include frontends/verilog/Makefile.inc
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include frontends/ilang/Makefile.inc
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include frontends/ast/Makefile.inc
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include frontends/blif/Makefile.inc
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include $(YOSYS_SRC)/frontends/verilog/Makefile.inc
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include $(YOSYS_SRC)/frontends/ilang/Makefile.inc
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include $(YOSYS_SRC)/frontends/ast/Makefile.inc
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include $(YOSYS_SRC)/frontends/blif/Makefile.inc
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OBJS += passes/hierarchy/hierarchy.o
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OBJS += passes/cmds/select.o
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@ -597,14 +597,14 @@ OBJS += passes/cmds/cover.o
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OBJS += passes/cmds/design.o
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OBJS += passes/cmds/plugin.o
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include passes/proc/Makefile.inc
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include passes/opt/Makefile.inc
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include passes/techmap/Makefile.inc
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include $(YOSYS_SRC)/passes/proc/Makefile.inc
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include $(YOSYS_SRC)/passes/opt/Makefile.inc
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include $(YOSYS_SRC)/passes/techmap/Makefile.inc
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include backends/verilog/Makefile.inc
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include backends/ilang/Makefile.inc
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include $(YOSYS_SRC)/backends/verilog/Makefile.inc
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include $(YOSYS_SRC)/backends/ilang/Makefile.inc
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include techlibs/common/Makefile.inc
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include $(YOSYS_SRC)/techlibs/common/Makefile.inc
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endif
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