riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,873 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

63 Commits

Author SHA1 Message Date
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung 52355f5185 Use more ID::{A,B,Y,blackbox,whitebox} 2019-08-15 14:50:10 -07:00
Clifford Wolf 6995914f3f Use ID() macro in all of passes/opt/ 
This was obtained by running the following SED command in passes/opt/
and then using "meld foo.cc foo.cc.orig" to manually fix all resulting
compiler errors.

sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Bogdan Vukobratovic 3225bfb984 Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too 2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic 35fa7b3057 Fix memory leak when one of multiple DFF cells is removed in opt_rmdff 
When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
 2019-06-27 22:02:12 +02:00
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 13:44:21 +02:00
Bogdan Vukobratovic 8451cbea89 Move netlist helper module to passes/opt for the time being 2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic 53695e6729 Prepare for situation when port of the signal cannot be found 2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic 291b36afeb Some cleanup, revert sat.cc 2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic 8665f48879 Implement disconnection of constant register bits 2019-06-13 19:35:37 +02:00
Bogdan Vukobratovic d69989b8d2 Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
Bogdan Vukobratovic 9892df17ef Generate satgen instance instead of calling sat pass 2019-06-11 11:47:13 +02:00
Eddie Hung feb2ddb52b Fix typo in opt_rmdff 2019-06-05 14:08:14 -07:00
Bogdan Vukobratovic 9a468f81c4 Optimizing DFFs whose initial value prevents their value from changing 
This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
 2019-05-28 08:48:21 +02:00
Eddie Hung d4fb6cac7c Revert enable check 2019-05-25 12:55:57 -07:00
Eddie Hung 822d0b7789 opt_rmdff to optimise even in presence of enable signal, even removing 2019-05-24 18:30:51 -07:00
Eddie Hung 0d66103cbb Add comments 2019-05-24 16:33:10 -07:00
Eddie Hung 357b1de6bc Resolve @cliffordwolf review, set even if !has_init 2019-05-24 16:15:22 -07:00
Eddie Hung 5ac7e38d0a Fix spacing 2019-05-23 12:58:30 -07:00
Eddie Hung 50ed34a6d0 opt_rmdff to work on $dffe and $_DFFE_* 2019-05-23 11:26:18 -07:00
Clifford Wolf 2da4c9c8f0 Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:49:45 +01:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf fba499b866 Fix opt_rmdff handling of $dlatchsr 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 11:46:05 +01:00
Clifford Wolf c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf 007f29b9c2 Add support for set-reset cell variants to opt_rmdff 2017-08-09 13:29:52 +02:00
Clifford Wolf c4a7958f70 Add handling of constant reset signals to opt_rmdff 2017-08-06 13:27:18 +02:00
Clifford Wolf e6cc67b46f Fix handling of init attributes with strange width 2017-02-09 16:06:58 +01:00
Clifford Wolf 7481ba4750 Improve opt_rmdff support for $dlatch cells 2017-01-31 10:15:04 +01:00
Clifford Wolf 2ef454c3f5 Added opt_rmdff support for $ff cells 2016-10-14 13:02:36 +02:00
Clifford Wolf ed519f578e Added "opt_rmdff -keepdc" 2016-09-30 17:02:38 +02:00
Clifford Wolf 4ea7054b56 Improved init spec handling in opt_rmdff, modernized the code a bit 2016-08-30 01:34:04 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf f43815054e Properly clean up unused "init" attributes 2015-08-18 13:50:15 +02:00
Clifford Wolf 2a613b1b66 Some cleanups in opt_rmdff 2015-07-25 12:09:57 +02:00
Clifford Wolf 914ae3401e Improved $adff simplification 2015-07-24 14:12:50 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 4b6221478e Added simple $dlatch support to opt_rmdff 2015-05-23 09:45:48 +02:00
Clifford Wolf 9041f34233 Improved handling of init values in opt_rmdff 
based on a patch by Mingyu Gao, user gaomy3832 on github
 2015-04-18 08:04:31 +02:00
Clifford Wolf 18cb8b4636 Don't be too smart with $dff cells with "init" attribute on out signal 2014-10-16 11:49:31 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00