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4737 Commits

Author SHA1 Message Date
Clifford Wolf e112d2fbf5 Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-06 16:35:59 +01:00
Eddie Hung 3f0bb441f8 Add tests 2019-02-04 16:46:24 -08:00
whitequark da65e1e8d9 write_verilog: correctly emit asynchronous transparent ports. 
This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.
 2019-01-29 02:24:00 +00:00
Clifford Wolf 266511b29e
Merge pull request #798 from mmicko/master 
Fixed Anlogic simulation model
 2019-01-27 09:25:18 +01:00
Clifford Wolf 81581f24fc
Merge pull request #800 from whitequark/write_verilog_tribuf 
write_verilog: write $tribuf cell as ternary
 2019-01-27 09:23:41 +01:00
Clifford Wolf bf798a9020 Merge branch 'whitequark-write_verilog_keyword' 2019-01-27 09:17:29 +01:00
Clifford Wolf 9666cca9dd Remove asicworld tests for (unsupported) switch-level modelling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-27 09:17:02 +01:00
whitequark 3d7925ad9f write_verilog: write $tribuf cell as ternary. 2019-01-27 00:24:06 +00:00
whitequark 42c47a83da write_verilog: escape names that match SystemVerilog keywords. 2019-01-27 00:03:53 +00:00
David Shah c82aa49d9e
Merge pull request #796 from whitequark/proc_clean_typo 
proc_clean: fix critical typo
 2019-01-25 21:33:06 +00:00
Miodrag Milanovic 0de328da8f Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
whitequark 58d059ccb7 proc_clean: fix critical typo. 2019-01-23 22:08:38 +00:00
David Shah 549b8e74b2 ecp5: Support for flipflop initialisation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-22 16:02:56 +00:00
David Shah ee8c9e854f ecp5: Add LSRMODE to flipflops for PRLD support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:35:22 +00:00
David Shah d8003e87d1 ecp5: More blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:34:34 +00:00
David Shah 01ea72f53a ecp5: Increase threshold for ALU mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:33:47 +00:00
Clifford Wolf c4b61f2d69
Merge pull request #793 from whitequark/proc_clean_fix_fully_def 
proc_clean: fix fully def check to consider compare/signal length
 2019-01-19 09:31:17 +01:00
whitequark 95b6c35882 proc_clean: fix fully def check to consider compare/signal length. 
Fixes #790.
 2019-01-18 23:22:19 +00:00
Clifford Wolf f3556e9f7a Cleanups in igloo2 example design 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 14:54:04 +01:00
Clifford Wolf db5765b443 Add SF2 IO buffer insertion 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 14:38:37 +01:00
Clifford Wolf 9b277fc21e Improve Igloo2 example 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 13:35:52 +01:00
Clifford Wolf 841ca74c90 Add "synth_sf2 -vlog", fix "synth_sf2 -edif" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 13:33:45 +01:00
Clifford Wolf 54dc33b905 Add "write_edif -gndvccy" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 13:33:11 +01:00
Clifford Wolf 8ddec5d882 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf 5216735210 Progress in pmgen, add pmgen README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf 55ac030382 Fix pmgen "reject" statement 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf d45379936b Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf 1f8e76f993 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf b9545aa0e1 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf ad69c668ce Add mockup .pmg (pattern matcher generator) file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf e70ebe557c Add optional nullstr argument to log_id() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:06:48 +01:00
Clifford Wolf 6c5049f016 Fix handling of $shiftx in Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 10:55:27 +01:00
Clifford Wolf 1d82a88e94
Merge pull request #788 from whitequark/master 
Document $tribuf and some gates
 2019-01-15 09:52:01 +01:00
Clifford Wolf 0994cfce7b
Merge pull request #787 from whitequark/flowmap_relax 
flowmap: implement depth relaxation
 2019-01-15 09:50:58 +01:00
whitequark fc2dd7ec8e manual: document some gates. 2019-01-14 16:17:25 +00:00
whitequark 7a45122168 manual: explain $tribuf cell. 2019-01-14 16:08:58 +00:00
Clifford Wolf 2a2e0a4722 Improve igloo2 example 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-08 20:16:36 +01:00
whitequark e792bd56b7 flowmap: clean up terminology. 
* "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.
 2019-01-08 02:05:06 +00:00
whitequark 211c26a4c9 flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00
Clifford Wolf f042559e9d Fix typo in manual 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:07:28 +01:00
Clifford Wolf 8a63fc51d3 Bugfix in $memrd sharing 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:04:47 +01:00
Clifford Wolf dbd51d7bda
Merge pull request #782 from whitequark/flowmap_dfs 
flowmap: construct a max-volume max-flow min-cut, not just any one
 2019-01-07 09:47:57 +01:00
Clifford Wolf b5f6e786ea Switch "bugpoint" from system() to run_command() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 09:45:21 +01:00
Clifford Wolf d35858078d
Merge pull request #783 from whitequark/bugpoint 
bugpoint: new pass
 2019-01-07 09:42:17 +01:00
whitequark a342d6db49 bugpoint: new pass. 
A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
 2019-01-07 03:13:19 +00:00
whitequark 8b44198e23 flowmap: construct a max-volume max-flow min-cut, not just any one. 2019-01-06 19:51:37 +00:00
Clifford Wolf a2c51d50fb
Merge pull request #780 from phire/rename_from_wire 
Rename cells based on the wires they drive.
 2019-01-06 11:35:31 +01:00
Scott Mansell 62c90c4e17 Rename cells based on the wires they drive. 2019-01-06 19:00:16 +13:00
Clifford Wolf f589ce86ba Add skeleton Yosys-Libero igloo2 example project 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 17:02:01 +01:00
Clifford Wolf 17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00