mirror of https://github.com/YosysHQ/yosys.git
Improve igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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/example.edn
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/netlist.edn
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/netlist.v
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/work
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read_verilog example.v
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synth_sf2 -top top -edif example.edn
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synth_sf2 -top top -edif netlist.edn
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write_verilog netlist.v
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@ -9,6 +9,27 @@ new_project \
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-speed -1 \
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-hdl VERILOG
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import_files -edif {example.edn}
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run_tool –name {COMPILE}
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run_tool –name {PLACEROUTEN}
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# import_files -edif "[pwd]/netlist.edn"
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import_files -hdl_source "[pwd]/netlist.v"
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set_root top
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save_project
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puts "**> SYNTHESIZE"
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run_tool -name {SYNTHESIZE}
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puts "<** SYNTHESIZE"
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puts "**> COMPILE"
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run_tool -name {COMPILE}
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puts "<** COMPILE"
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puts "**> PLACEROUTE"
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run_tool -name {PLACEROUTE}
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puts "<** PLACEROUTE"
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# puts "**> export_bitstream"
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# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
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# puts "<** export_bitstream"
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exit 0
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#!/bin/bash
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set -ex
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rm -rf work
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yosys example.ys
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LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
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