github-actions[bot]
d11cb6901f
Bump version
2023-01-30 00:14:47 +00:00
Dag Lem
26db5a11d3
Resolve struct member package types
2023-01-29 13:51:44 -05:00
Dag Lem
db13c6df2b
Handle struct members of union type ( #3641 )
2023-01-29 13:45:45 -05:00
github-actions[bot]
541fdffff2
Bump version
2023-01-26 00:16:37 +00:00
Miodrag Milanović
b9155a574e
Merge pull request #3647 from jix/formalff-hierarchy-fix
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formalff: Fix crash with _NOT_ gates in -hierarchy mode
2023-01-25 13:37:44 +01:00
Jannis Harder
afac3f2c76
formalff: Fix crash with _NOT_ gates in -hierarchy mode
2023-01-25 12:55:29 +01:00
github-actions[bot]
755b753e1a
Bump version
2023-01-24 00:16:28 +00:00
Miodrag Milanović
8180cc4325
Merge pull request #3624 from jix/sim_yw
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Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
Miodrag Milanović
245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes
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Fixes for some of clang scan-build detected issues
2023-01-23 16:24:22 +01:00
Miodrag Milanović
9bc9121b9e
Merge pull request #3636 from YosysHQ/log_plugin
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Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
2023-01-23 16:24:03 +01:00
gatecat
bfacaddca8
show: Remove left-in debug log_warning
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-23 13:54:07 +01:00
Miodrag Milanovic
200ffdccc5
Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
2023-01-20 16:09:42 +01:00
Miodrag Milanović
611f71c670
Merge pull request #3630 from yrabbit/gw1n4c-pll
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gowin: add a new type of PLL - PLLVR
2023-01-18 08:30:29 +01:00
github-actions[bot]
29e7756b0c
Bump version
2023-01-18 00:17:17 +00:00
Claire Xenia Wolf
bfc3c20cfb
Improve splitcells pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-01-18 00:31:29 +01:00
Miodrag Milanovic
6574553189
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
github-actions[bot]
956c4e485a
Bump version
2023-01-12 01:17:55 +00:00
N. Engelhardt
692a0fa33b
print filename in liberty log_header
2023-01-11 21:31:46 +01:00
Jannis Harder
d6c7aa0e3d
sim/formalff: Clock handling for yw cosim
2023-01-11 18:07:16 +01:00
Jannis Harder
7ddec5093f
sim: Improvements and fixes for yw cosim
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* Fixed $cover handling
* Improved sparse memory handling when writing traces
* JSON summary output
2023-01-11 18:07:16 +01:00
Jannis Harder
636b9f2705
Support for BTOR witness to Yosys witness conversion
2023-01-11 18:07:16 +01:00
Jannis Harder
3e25e61778
aiger: Use new JSON code for writing aiger witness map files
2023-01-11 18:07:16 +01:00
Jannis Harder
29461ade17
Add json.{h,cc} for pretty printing JSON
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Avoids errors in trailing comma handling, broken indentation and
improper escaping that is common when building JSON by manually
concatenating strings.
2023-01-11 18:07:16 +01:00
Jannis Harder
dda972a148
sim: New -append option for Yosys witness cosim
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This is needed to support SBY's append option.
2023-01-11 18:07:16 +01:00
Jannis Harder
2dd5652215
sim: Add Yosys witness (.yw) cosimulation
2023-01-11 18:07:16 +01:00
Jannis Harder
1494cfff00
New kernel/yw.{h,cc} to support reading Yosys witness files
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This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
2023-01-11 18:07:16 +01:00
Jannis Harder
f6458bab70
sim: Only check formal cells during gclk simulation updates
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This is required for compatibility with non-multiclock formal semantics.
2023-01-11 18:07:16 +01:00
Jannis Harder
9c6198a827
sim: Internal API to set $initstate
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This is not yet added to any of the simulation drivers.
2023-01-11 18:07:16 +01:00
Jannis Harder
44b26d5c6d
sim: Emit used memory addresses as signals to output traces
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This matches the behavior of smtbmc.
This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
2023-01-11 18:07:16 +01:00
Jannis Harder
5042600c0d
xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef
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This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
2023-01-11 18:07:16 +01:00
Jannis Harder
673ad561b8
smt2: Treat bweqx as xnor
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Without x-bits they are equivalent
2023-01-11 18:07:16 +01:00
Jannis Harder
62afe61779
smt2: Directly implement bwmux instead of using bwmuxmap
2023-01-11 18:07:16 +01:00
N. Engelhardt
4173daa708
Merge pull request #3605 from gadfort/stat-json-area
2023-01-11 16:41:44 +01:00
Claire Xen
2e3c08adc4
Merge pull request #3570 from YosysHQ/claire/eqystuff
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Various Changes for EQY
2023-01-11 16:37:52 +01:00
Claire Xen
843f329b96
Merge branch 'master' into claire/eqystuff
2023-01-11 16:33:08 +01:00
Jannis Harder
5abaa59080
Merge pull request #3537 from jix/xprop
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New xprop pass
2023-01-11 16:26:04 +01:00
N. Engelhardt
d742d063d4
remove template declaration that stops function from being used
2023-01-11 16:09:05 +01:00
N. Engelhardt
41ce00e82a
Merge pull request #3620 from YosysHQ/gcc48_remove
2023-01-11 16:05:56 +01:00
Miodrag Milanovic
4fc5207b1e
Add deprecation info to changelog
2023-01-11 11:23:23 +01:00
Miodrag Milanovic
5801152779
Deprecate gcc-4.8
2023-01-11 09:54:19 +01:00
Claire Xenia Wolf
6d56d4ecfc
Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff
2023-01-11 04:10:12 +01:00
YRabbit
d6a1e022e1
gowin: add a new type of PLL - PLLVR
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This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-11 11:41:29 +10:00
github-actions[bot]
7b476996df
Bump version
2023-01-11 01:16:47 +00:00
Miodrag Milanović
2677569d48
Merge pull request #3616 from YosysHQ/register_error
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Display error instead of assertion when pass exists
2023-01-10 11:38:57 +01:00
Miodrag Milanović
2b622258a2
Merge pull request #3615 from YosysHQ/qbfsat_cvc5
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qbfsat support for cvc5, fixes #3608
2023-01-10 11:38:16 +01:00
Miodrag Milanovic
40282576b0
Display error instead of assertion when pass exists
2023-01-09 17:02:56 +01:00
Miodrag Milanovic
e3c0fd8b10
qbfsat support for cvc5, fixes #3608
2023-01-09 16:14:01 +01:00
github-actions[bot]
f2c689403a
Bump version
2023-01-05 00:16:46 +00:00
gatecat
7bac1920b2
nexus: Fix BRAM write enable in PDP mode
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-04 17:59:36 +01:00
github-actions[bot]
d3216593da
Bump version
2023-01-04 00:16:03 +00:00