Merge pull request #3570 from YosysHQ/claire/eqystuff

Various Changes for EQY
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Claire Xen 2023-01-11 16:37:52 +01:00 committed by GitHub
commit 2e3c08adc4
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8 changed files with 1380 additions and 17 deletions

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@ -7,12 +7,14 @@ OBJS += passes/cmds/delete.o
OBJS += passes/cmds/design.o
OBJS += passes/cmds/select.o
OBJS += passes/cmds/show.o
OBJS += passes/cmds/viz.o
OBJS += passes/cmds/rename.o
OBJS += passes/cmds/autoname.o
OBJS += passes/cmds/connect.o
OBJS += passes/cmds/scatter.o
OBJS += passes/cmds/setundef.o
OBJS += passes/cmds/splitnets.o
OBJS += passes/cmds/splitcells.o
OBJS += passes/cmds/stat.o
OBJS += passes/cmds/setattr.o
OBJS += passes/cmds/copy.o

199
passes/cmds/splitcells.cc Normal file
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@ -0,0 +1,199 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SplitcellsWorker
{
Module *module;
SigMap sigmap;
dict<SigBit, tuple<IdString,IdString,int>> bit_drivers_db;
dict<SigBit, pool<tuple<IdString,IdString,int>>> bit_users_db;
SplitcellsWorker(Module *module) : module(module), sigmap(module)
{
for (auto cell : module->cells()) {
for (auto conn : cell->connections()) {
if (!cell->output(conn.first)) continue;
for (int i = 0; i < GetSize(conn.second); i++) {
SigBit bit(sigmap(conn.second[i]));
bit_drivers_db[bit] = tuple<IdString,IdString,int>(cell->name, conn.first, i);
}
}
}
for (auto cell : module->cells()) {
for (auto conn : cell->connections()) {
if (!cell->input(conn.first)) continue;
for (int i = 0; i < GetSize(conn.second); i++) {
SigBit bit(sigmap(conn.second[i]));
if (!bit_drivers_db.count(bit)) continue;
bit_users_db[bit].insert(tuple<IdString,IdString,int>(cell->name,
conn.first, i-std::get<2>(bit_drivers_db[bit])));
}
}
}
for (auto wire : module->wires()) {
if (!wire->name.isPublic()) continue;
SigSpec sig(sigmap(wire));
for (int i = 0; i < GetSize(sig); i++) {
SigBit bit(sig[i]);
if (!bit_drivers_db.count(bit)) continue;
bit_users_db[bit].insert(tuple<IdString,IdString,int>(wire->name,
IdString(), i-std::get<2>(bit_drivers_db[bit])));
}
}
}
int split(Cell *cell, const std::string &format)
{
if (!cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor")) return 0;
SigSpec outsig = sigmap(cell->getPort(ID::Y));
if (GetSize(outsig) <= 1) return 0;
std::vector<int> slices;
slices.push_back(0);
int width = GetSize(outsig);
width = std::min(width, GetSize(cell->getPort(ID::A)));
if (cell->hasPort(ID::B))
width = std::min(width, GetSize(cell->getPort(ID::B)));
for (int i = 1; i < width; i++) {
auto &last_users = bit_users_db[outsig[slices.back()]];
auto &this_users = bit_users_db[outsig[i]];
if (last_users != this_users) slices.push_back(i);
}
if (GetSize(slices) <= 1) return 0;
slices.push_back(GetSize(outsig));
log("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
for (int i = 1; i < GetSize(slices); i++)
{
int slice_msb = slices[i]-1;
int slice_lsb = slices[i-1];
IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ?
stringf("%c%d%c", format[0], slice_lsb, format[1]) :
stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])));
Cell *slice = module->addCell(slice_name, cell);
auto slice_signal = [&](SigSpec old_sig) -> SigSpec {
SigSpec new_sig;
for (int i = 0; i < GetSize(old_sig); i += GetSize(outsig)) {
int offset = i+slice_lsb;
int length = std::min(GetSize(old_sig)-offset, slice_msb-slice_lsb+1);
new_sig.append(old_sig.extract(offset, length));
}
return new_sig;
};
slice->setPort(ID::A, slice_signal(slice->getPort(ID::A)));
if (slice->hasParam(ID::A_WIDTH))
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A)));
if (slice->hasPort(ID::B)) {
slice->setPort(ID::B, slice_signal(slice->getPort(ID::B)));
if (slice->hasParam(ID::B_WIDTH))
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B)));
}
slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y)));
if (slice->hasParam(ID::Y_WIDTH))
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y)));
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Y)));
}
module->remove(cell);
return GetSize(slices)-1;
}
};
struct SplitcellsPass : public Pass {
SplitcellsPass() : Pass("splitcells", "split up multi-bit cells") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" splitcells [options] [selection]\n");
log("\n");
log("This command splits multi-bit cells into smaller chunks, based on usage of the\n");
log("cell output bits.\n");
log("\n");
log("This command operates only in cells such as $or, $and, and $mux, that are easily\n");
log("cut into bit-slices.\n");
log("\n");
log(" -format char1[char2[char3]]\n");
log(" the first char is inserted between the cell name and the bit index, the\n");
log(" second char is appended to the cell name. e.g. -format () creates cell\n");
log(" names like 'mycell(42)'. the 3rd character is the range separation\n");
log(" character when creating multi-bit cells. the default is '[]:'.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string format;
log_header(design, "Executing SPLITCELLS pass (splitting up multi-bit cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-format" && argidx+1 < args.size()) {
format = args[++argidx];
continue;
}
break;
}
extra_args(args, argidx, design);
if (GetSize(format) < 1) format += "[";
if (GetSize(format) < 2) format += "]";
if (GetSize(format) < 3) format += ":";
for (auto module : design->selected_modules())
{
SplitcellsWorker worker(module);
int count_split_pre = 0;
int count_split_post = 0;
for (auto cell : module->selected_cells()) {
int n = worker.split(cell, format);
count_split_pre += (n != 0);
count_split_post += n;
}
if (count_split_pre)
log("Split %d cells in module %s into %d cell slices.\n",
count_split_pre, log_id(module), count_split_post);
}
}
} SplitnetsPass;
PRIVATE_NAMESPACE_END

1081
passes/cmds/viz.cc Normal file

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@ -33,6 +33,7 @@ struct XpropOptions
{
bool split_inputs = false;
bool split_outputs = false;
bool split_public = false;
bool assume_encoding = false;
bool assert_encoding = false;
bool assume_def_inputs = false;
@ -966,7 +967,7 @@ struct XpropWorker
if (!options.split_inputs && !options.split_outputs)
return;
vector<IdString> new_ports;
int port_id = 1;
for (auto port : module->ports) {
auto wire = module->wire(port);
@ -982,16 +983,21 @@ struct XpropWorker
wire_d->port_input = wire->port_input;
wire_d->port_output = wire->port_output;
wire_d->port_id = GetSize(new_ports) + 1;
wire_d->port_id = port_id++;
wire_x->port_input = wire->port_input;
wire_x->port_output = wire->port_output;
wire_x->port_id = GetSize(new_ports) + 2;
wire_x->port_id = port_id++;
if (wire->port_output) {
auto enc = encoded(wire);
module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x);
if (options.split_public) {
// Need to hide the original wire so split_public doesn't try to split it again
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
}
} else {
auto enc = encoded(wire, true);
@ -1003,21 +1009,37 @@ struct XpropWorker
wire->port_input = wire->port_output = false;
wire->port_id = 0;
new_ports.push_back(port_d);
new_ports.push_back(port_x);
continue;
}
}
wire->port_id = GetSize(new_ports) + 1;
new_ports.push_back(port);
wire->port_id = port_id++;
}
module->ports = new_ports;
module->fixup_ports();
}
void split_public()
{
if (!options.split_public)
return;
for (auto wire : module->selected_wires()) {
if (wire->port_input || wire->port_output || !wire->name.isPublic())
continue;
auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()));
auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()));
auto wire_d = module->addWire(name_d, GetSize(wire));
auto wire_x = module->addWire(name_x, GetSize(wire));
auto enc = encoded(wire);
module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x);
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
}
}
void encode_remaining()
{
pool<Wire *> enc_undriven_wires;
@ -1083,6 +1105,13 @@ struct XpropPass : public Pass {
log(" the corresponding bit in <portname>_d is ignored for inputs and\n");
log(" guaranteed to be 0 for outputs.\n");
log("\n");
log(" -split-public\n");
log(" Replace each public non-port wire with two new wires, one carrying the\n");
log(" defined values (named <wirename>_d) and one carrying the mask of which\n");
log(" bits are x (named <wirename>_x). When a bit in the <portname>_x is set\n");
log(" the corresponding bit in <wirename>_d is guaranteed to be 0 for\n");
log(" outputs.\n");
log("\n");
log(" -assume-encoding\n");
log(" Add encoding invariants as assumptions. This can speed up formal\n");
log(" verification tasks.\n");
@ -1129,6 +1158,10 @@ struct XpropPass : public Pass {
options.split_outputs = true;
continue;
}
if (args[argidx] == "-split-public") {
options.split_public = true;
continue;
}
if (args[argidx] == "-assume-encoding") {
options.assume_encoding = true;
continue;
@ -1188,6 +1221,8 @@ struct XpropPass : public Pass {
worker.process_cells();
log_debug("Splitting ports.\n");
worker.split_ports();
log_debug("Splitting public signals.\n");
worker.split_public();
log_debug("Encode remaining signals.\n");
worker.encode_remaining();

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@ -52,6 +52,7 @@ struct UniquifyPass : public Pass {
// flag_check = true;
// continue;
// }
break;
}
extra_args(args, argidx, design);

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@ -144,8 +144,16 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
{
if (gold_cross_ports.count(gold_wire))
{
RTLIL::Wire *w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
gold_cell->setPort(gold_wire->name, w);
if (flag_ignore_gold_x) {
RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w));
for (int i = 0; i < GetSize(w); i++)
miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]);
RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x);
RTLIL::SigSpec w_masked = miter_module->And(NEW_ID, w, miter_module->Not(NEW_ID, w_x));
w = miter_module->And(NEW_ID, w_any, w_masked);
}
gate_cell->setPort(gold_wire->name, w);
continue;
}

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@ -685,10 +685,11 @@ struct SimInstance
void writeback(pool<Module*> &wbmods)
{
if (wbmods.count(module))
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
wbmods.insert(module);
if (!ff_database.empty() || !mem_database.empty()) {
if (wbmods.count(module))
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
wbmods.insert(module);
}
for (auto wire : module->wires())
wire->attributes.erase(ID::init);

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@ -36,12 +36,16 @@ struct InsbufPass : public Pass {
log(" Use the given cell type instead of $_BUF_. (Notice that the next\n");
log(" call to \"clean\" will remove all $_BUF_ in the design.)\n");
log("\n");
log(" -chain\n");
log(" Chain buffer cells\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
bool chain_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -53,6 +57,10 @@ struct InsbufPass : public Pass {
out_portname = RTLIL::escape_id(args[++argidx]);
continue;
}
if (arg == "-chain") {
chain_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -60,6 +68,8 @@ struct InsbufPass : public Pass {
for (auto module : design->selected_modules())
{
std::vector<RTLIL::SigSig> new_connections;
pool<Cell*> bufcells;
SigMap sigmap;
for (auto &conn : module->connections())
{
@ -70,22 +80,48 @@ struct InsbufPass : public Pass {
SigBit lhs = conn.first[i];
SigBit rhs = conn.second[i];
if (lhs.wire && !design->selected(module, lhs.wire)) {
if (!lhs.wire || !design->selected(module, lhs.wire)) {
new_conn.first.append(lhs);
new_conn.second.append(rhs);
log("Skip %s: %s -> %s\n", log_id(module), log_signal(rhs), log_signal(lhs));
continue;
}
if (chain_mode && rhs.wire) {
rhs = sigmap(rhs);
SigBit outbit = sigmap(lhs);
sigmap.add(lhs, rhs);
sigmap.add(outbit);
}
Cell *cell = module->addCell(NEW_ID, celltype);
cell->setPort(in_portname, rhs);
cell->setPort(out_portname, lhs);
log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
log("Add %s/%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
bufcells.insert(cell);
}
if (GetSize(new_conn.first))
new_connections.push_back(new_conn);
}
if (chain_mode) {
for (auto &cell : module->selected_cells()) {
if (bufcells.count(cell))
continue;
for (auto &port : cell->connections())
if (cell->input(port.first)) {
auto s = sigmap(port.second);
if (s == port.second)
continue;
log("Rewrite %s/%s/%s: %s -> %s\n", log_id(module), log_id(cell),
log_id(port.first), log_signal(port.second), log_signal(s));
cell->setPort(port.first, s);
}
}
}
module->new_connections(new_connections);
}
}