mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3570 from YosysHQ/claire/eqystuff
Various Changes for EQY
This commit is contained in:
commit
2e3c08adc4
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@ -7,12 +7,14 @@ OBJS += passes/cmds/delete.o
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OBJS += passes/cmds/design.o
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OBJS += passes/cmds/select.o
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OBJS += passes/cmds/show.o
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OBJS += passes/cmds/viz.o
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OBJS += passes/cmds/rename.o
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OBJS += passes/cmds/autoname.o
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OBJS += passes/cmds/connect.o
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OBJS += passes/cmds/scatter.o
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OBJS += passes/cmds/setundef.o
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OBJS += passes/cmds/splitnets.o
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OBJS += passes/cmds/splitcells.o
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OBJS += passes/cmds/stat.o
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OBJS += passes/cmds/setattr.o
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OBJS += passes/cmds/copy.o
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@ -0,0 +1,199 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SplitcellsWorker
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{
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Module *module;
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SigMap sigmap;
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dict<SigBit, tuple<IdString,IdString,int>> bit_drivers_db;
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dict<SigBit, pool<tuple<IdString,IdString,int>>> bit_users_db;
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SplitcellsWorker(Module *module) : module(module), sigmap(module)
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{
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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bit_drivers_db[bit] = tuple<IdString,IdString,int>(cell->name, conn.first, i);
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}
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}
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}
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->input(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(cell->name,
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conn.first, i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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for (auto wire : module->wires()) {
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if (!wire->name.isPublic()) continue;
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SigSpec sig(sigmap(wire));
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit(sig[i]);
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(wire->name,
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IdString(), i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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int split(Cell *cell, const std::string &format)
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{
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if (!cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor")) return 0;
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SigSpec outsig = sigmap(cell->getPort(ID::Y));
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if (GetSize(outsig) <= 1) return 0;
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std::vector<int> slices;
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slices.push_back(0);
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int width = GetSize(outsig);
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width = std::min(width, GetSize(cell->getPort(ID::A)));
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if (cell->hasPort(ID::B))
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width = std::min(width, GetSize(cell->getPort(ID::B)));
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for (int i = 1; i < width; i++) {
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auto &last_users = bit_users_db[outsig[slices.back()]];
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auto &this_users = bit_users_db[outsig[i]];
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if (last_users != this_users) slices.push_back(i);
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}
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if (GetSize(slices) <= 1) return 0;
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slices.push_back(GetSize(outsig));
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log("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
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for (int i = 1; i < GetSize(slices); i++)
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{
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int slice_msb = slices[i]-1;
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int slice_lsb = slices[i-1];
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IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ?
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stringf("%c%d%c", format[0], slice_lsb, format[1]) :
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stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])));
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Cell *slice = module->addCell(slice_name, cell);
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auto slice_signal = [&](SigSpec old_sig) -> SigSpec {
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SigSpec new_sig;
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for (int i = 0; i < GetSize(old_sig); i += GetSize(outsig)) {
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int offset = i+slice_lsb;
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int length = std::min(GetSize(old_sig)-offset, slice_msb-slice_lsb+1);
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new_sig.append(old_sig.extract(offset, length));
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}
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return new_sig;
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};
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slice->setPort(ID::A, slice_signal(slice->getPort(ID::A)));
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if (slice->hasParam(ID::A_WIDTH))
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slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A)));
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if (slice->hasPort(ID::B)) {
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slice->setPort(ID::B, slice_signal(slice->getPort(ID::B)));
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if (slice->hasParam(ID::B_WIDTH))
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slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B)));
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}
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slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y)));
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if (slice->hasParam(ID::Y_WIDTH))
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slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y)));
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if (slice->hasParam(ID::WIDTH))
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slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
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log(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Y)));
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}
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module->remove(cell);
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return GetSize(slices)-1;
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}
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};
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struct SplitcellsPass : public Pass {
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SplitcellsPass() : Pass("splitcells", "split up multi-bit cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splitcells [options] [selection]\n");
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log("\n");
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log("This command splits multi-bit cells into smaller chunks, based on usage of the\n");
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log("cell output bits.\n");
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log("\n");
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log("This command operates only in cells such as $or, $and, and $mux, that are easily\n");
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log("cut into bit-slices.\n");
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log("\n");
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log(" -format char1[char2[char3]]\n");
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log(" the first char is inserted between the cell name and the bit index, the\n");
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log(" second char is appended to the cell name. e.g. -format () creates cell\n");
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log(" names like 'mycell(42)'. the 3rd character is the range separation\n");
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log(" character when creating multi-bit cells. the default is '[]:'.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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std::string format;
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log_header(design, "Executing SPLITCELLS pass (splitting up multi-bit cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-format" && argidx+1 < args.size()) {
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format = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (GetSize(format) < 1) format += "[";
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if (GetSize(format) < 2) format += "]";
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if (GetSize(format) < 3) format += ":";
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for (auto module : design->selected_modules())
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{
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SplitcellsWorker worker(module);
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int count_split_pre = 0;
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int count_split_post = 0;
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for (auto cell : module->selected_cells()) {
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int n = worker.split(cell, format);
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count_split_pre += (n != 0);
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count_split_post += n;
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}
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if (count_split_pre)
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log("Split %d cells in module %s into %d cell slices.\n",
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count_split_pre, log_id(module), count_split_post);
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}
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}
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} SplitnetsPass;
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PRIVATE_NAMESPACE_END
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File diff suppressed because it is too large
Load Diff
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@ -33,6 +33,7 @@ struct XpropOptions
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{
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bool split_inputs = false;
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bool split_outputs = false;
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bool split_public = false;
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bool assume_encoding = false;
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bool assert_encoding = false;
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bool assume_def_inputs = false;
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@ -966,7 +967,7 @@ struct XpropWorker
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if (!options.split_inputs && !options.split_outputs)
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return;
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vector<IdString> new_ports;
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int port_id = 1;
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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@ -982,16 +983,21 @@ struct XpropWorker
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wire_d->port_input = wire->port_input;
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wire_d->port_output = wire->port_output;
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wire_d->port_id = GetSize(new_ports) + 1;
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wire_d->port_id = port_id++;
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wire_x->port_input = wire->port_input;
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wire_x->port_output = wire->port_output;
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wire_x->port_id = GetSize(new_ports) + 2;
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wire_x->port_id = port_id++;
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if (wire->port_output) {
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auto enc = encoded(wire);
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module->connect(wire_d, enc.is_1);
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module->connect(wire_x, enc.is_x);
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if (options.split_public) {
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// Need to hide the original wire so split_public doesn't try to split it again
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module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
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}
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} else {
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auto enc = encoded(wire, true);
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@ -1003,21 +1009,37 @@ struct XpropWorker
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wire->port_input = wire->port_output = false;
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wire->port_id = 0;
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new_ports.push_back(port_d);
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new_ports.push_back(port_x);
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continue;
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}
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}
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wire->port_id = GetSize(new_ports) + 1;
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new_ports.push_back(port);
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wire->port_id = port_id++;
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}
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module->ports = new_ports;
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module->fixup_ports();
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}
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void split_public()
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{
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if (!options.split_public)
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return;
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for (auto wire : module->selected_wires()) {
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if (wire->port_input || wire->port_output || !wire->name.isPublic())
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continue;
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auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()));
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auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()));
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auto wire_d = module->addWire(name_d, GetSize(wire));
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auto wire_x = module->addWire(name_x, GetSize(wire));
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auto enc = encoded(wire);
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module->connect(wire_d, enc.is_1);
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module->connect(wire_x, enc.is_x);
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module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
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}
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}
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void encode_remaining()
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{
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pool<Wire *> enc_undriven_wires;
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@ -1083,6 +1105,13 @@ struct XpropPass : public Pass {
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log(" the corresponding bit in <portname>_d is ignored for inputs and\n");
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log(" guaranteed to be 0 for outputs.\n");
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log("\n");
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log(" -split-public\n");
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log(" Replace each public non-port wire with two new wires, one carrying the\n");
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log(" defined values (named <wirename>_d) and one carrying the mask of which\n");
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log(" bits are x (named <wirename>_x). When a bit in the <portname>_x is set\n");
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log(" the corresponding bit in <wirename>_d is guaranteed to be 0 for\n");
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log(" outputs.\n");
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log("\n");
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log(" -assume-encoding\n");
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log(" Add encoding invariants as assumptions. This can speed up formal\n");
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log(" verification tasks.\n");
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@ -1129,6 +1158,10 @@ struct XpropPass : public Pass {
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options.split_outputs = true;
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continue;
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}
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if (args[argidx] == "-split-public") {
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options.split_public = true;
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continue;
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}
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if (args[argidx] == "-assume-encoding") {
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options.assume_encoding = true;
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continue;
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@ -1188,6 +1221,8 @@ struct XpropPass : public Pass {
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worker.process_cells();
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log_debug("Splitting ports.\n");
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worker.split_ports();
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log_debug("Splitting public signals.\n");
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worker.split_public();
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log_debug("Encode remaining signals.\n");
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worker.encode_remaining();
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|
|
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@ -52,6 +52,7 @@ struct UniquifyPass : public Pass {
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// flag_check = true;
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// continue;
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||||
// }
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break;
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}
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extra_args(args, argidx, design);
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|
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|
|
|
@ -144,8 +144,16 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
|
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{
|
||||
if (gold_cross_ports.count(gold_wire))
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{
|
||||
RTLIL::Wire *w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
|
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SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
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gold_cell->setPort(gold_wire->name, w);
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if (flag_ignore_gold_x) {
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||||
RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w));
|
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for (int i = 0; i < GetSize(w); i++)
|
||||
miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]);
|
||||
RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x);
|
||||
RTLIL::SigSpec w_masked = miter_module->And(NEW_ID, w, miter_module->Not(NEW_ID, w_x));
|
||||
w = miter_module->And(NEW_ID, w_any, w_masked);
|
||||
}
|
||||
gate_cell->setPort(gold_wire->name, w);
|
||||
continue;
|
||||
}
|
||||
|
|
|
@ -685,10 +685,11 @@ struct SimInstance
|
|||
|
||||
void writeback(pool<Module*> &wbmods)
|
||||
{
|
||||
if (wbmods.count(module))
|
||||
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
|
||||
|
||||
wbmods.insert(module);
|
||||
if (!ff_database.empty() || !mem_database.empty()) {
|
||||
if (wbmods.count(module))
|
||||
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
|
||||
wbmods.insert(module);
|
||||
}
|
||||
|
||||
for (auto wire : module->wires())
|
||||
wire->attributes.erase(ID::init);
|
||||
|
|
|
@ -36,12 +36,16 @@ struct InsbufPass : public Pass {
|
|||
log(" Use the given cell type instead of $_BUF_. (Notice that the next\n");
|
||||
log(" call to \"clean\" will remove all $_BUF_ in the design.)\n");
|
||||
log("\n");
|
||||
log(" -chain\n");
|
||||
log(" Chain buffer cells\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
|
||||
|
||||
IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
|
||||
bool chain_mode = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
@ -53,6 +57,10 @@ struct InsbufPass : public Pass {
|
|||
out_portname = RTLIL::escape_id(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
if (arg == "-chain") {
|
||||
chain_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
@ -60,6 +68,8 @@ struct InsbufPass : public Pass {
|
|||
for (auto module : design->selected_modules())
|
||||
{
|
||||
std::vector<RTLIL::SigSig> new_connections;
|
||||
pool<Cell*> bufcells;
|
||||
SigMap sigmap;
|
||||
|
||||
for (auto &conn : module->connections())
|
||||
{
|
||||
|
@ -70,22 +80,48 @@ struct InsbufPass : public Pass {
|
|||
SigBit lhs = conn.first[i];
|
||||
SigBit rhs = conn.second[i];
|
||||
|
||||
if (lhs.wire && !design->selected(module, lhs.wire)) {
|
||||
if (!lhs.wire || !design->selected(module, lhs.wire)) {
|
||||
new_conn.first.append(lhs);
|
||||
new_conn.second.append(rhs);
|
||||
log("Skip %s: %s -> %s\n", log_id(module), log_signal(rhs), log_signal(lhs));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (chain_mode && rhs.wire) {
|
||||
rhs = sigmap(rhs);
|
||||
SigBit outbit = sigmap(lhs);
|
||||
sigmap.add(lhs, rhs);
|
||||
sigmap.add(outbit);
|
||||
}
|
||||
|
||||
Cell *cell = module->addCell(NEW_ID, celltype);
|
||||
cell->setPort(in_portname, rhs);
|
||||
cell->setPort(out_portname, lhs);
|
||||
log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
|
||||
|
||||
log("Add %s/%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
|
||||
bufcells.insert(cell);
|
||||
}
|
||||
|
||||
if (GetSize(new_conn.first))
|
||||
new_connections.push_back(new_conn);
|
||||
}
|
||||
|
||||
if (chain_mode) {
|
||||
for (auto &cell : module->selected_cells()) {
|
||||
if (bufcells.count(cell))
|
||||
continue;
|
||||
for (auto &port : cell->connections())
|
||||
if (cell->input(port.first)) {
|
||||
auto s = sigmap(port.second);
|
||||
if (s == port.second)
|
||||
continue;
|
||||
log("Rewrite %s/%s/%s: %s -> %s\n", log_id(module), log_id(cell),
|
||||
log_id(port.first), log_signal(port.second), log_signal(s));
|
||||
cell->setPort(port.first, s);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
module->new_connections(new_connections);
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue