Clifford Wolf
|
c91570bde3
|
Mostly cosmetic changes to rtlil.h
|
2014-07-27 02:00:04 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
d7916a49af
|
New message for completion of build
|
2014-07-26 21:35:16 +02:00 |
Clifford Wolf
|
d68c993ed2
|
Changed more code to the new RTLIL::Wire constructors
|
2014-07-26 21:30:38 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
d49dec1f86
|
Added tests/various/.gitignore
|
2014-07-26 17:43:41 +02:00 |
Clifford Wolf
|
b21ebe1859
|
Added tests/various/submod_extract.ys
|
2014-07-26 17:22:18 +02:00 |
Clifford Wolf
|
267c615640
|
Added support for here documents
|
2014-07-26 17:21:40 +02:00 |
Clifford Wolf
|
3f4e3ca8ad
|
More RTLIL::Cell API usage cleanups
|
2014-07-26 16:14:02 +02:00 |
Clifford Wolf
|
97a59851a6
|
Added RTLIL::Cell::has(portname)
|
2014-07-26 16:11:28 +02:00 |
Clifford Wolf
|
a84cb04935
|
Merge automatic and manual code changes for new cell connections API
|
2014-07-26 16:00:30 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cd6574ecf6
|
Added some missing "const" in rtlil.h
|
2014-07-26 15:58:22 +02:00 |
Clifford Wolf
|
7ac9dc7f6e
|
Added RTLIL::Module::connections()
|
2014-07-26 15:58:21 +02:00 |
Clifford Wolf
|
b03aec6e32
|
Added RTLIL::Module::connect(const RTLIL::SigSig&)
|
2014-07-26 14:31:47 +02:00 |
Clifford Wolf
|
027819c7e8
|
Use "wget -N" in tests/vloghtb/run-test.sh
|
2014-07-26 14:08:43 +02:00 |
Clifford Wolf
|
b90f443338
|
Added "passed" message to make test targets
|
2014-07-26 14:08:20 +02:00 |
Clifford Wolf
|
3719281ed4
|
Automatically pack SigSpec on copy/assign
|
2014-07-26 13:59:30 +02:00 |
Clifford Wolf
|
e75e495c2b
|
Added new RTLIL::Cell port access methods
|
2014-07-26 12:22:58 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
665759fcee
|
Cosmetic fixes for "make abc"
|
2014-07-26 11:55:58 +02:00 |
Clifford Wolf
|
f8a68b8f55
|
Added "Checklist for adding internal cell types"
|
2014-07-26 11:23:43 +02:00 |
Clifford Wolf
|
4755e14e7b
|
Added copy-constructor-like module->addCell(name, other) method
|
2014-07-26 00:38:44 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
5826670009
|
Various RTLIL::SigSpec related code cleanups
|
2014-07-25 14:25:42 +02:00 |
Clifford Wolf
|
c762050e7f
|
Added RTLIL::SigSpec is_chunk()/as_chunk() API
|
2014-07-25 14:23:10 +02:00 |
Clifford Wolf
|
1834af5e53
|
Added "make vgtest"
|
2014-07-25 13:24:26 +02:00 |
Clifford Wolf
|
309d64d46a
|
Fixed two memory leaks in ast simplify
|
2014-07-25 13:24:10 +02:00 |
Clifford Wolf
|
50f22ff30c
|
Renamed some of the test cases in tests/simple to avoid name collisions
|
2014-07-25 13:01:45 +02:00 |
Clifford Wolf
|
0520bfea89
|
Fixed memory corruption in "opt_reduce" pass
|
2014-07-25 12:49:51 +02:00 |
Clifford Wolf
|
c4e4f79a2a
|
Disabled cover() for non-linux builds
|
2014-07-25 12:27:36 +02:00 |
Clifford Wolf
|
a8706b73a2
|
Added more stuff to checklist
|
2014-07-25 12:16:23 +02:00 |
Clifford Wolf
|
1488bc0c4f
|
Updated verific build/test instructions
|
2014-07-25 12:16:03 +02:00 |
Clifford Wolf
|
91bf0c90c8
|
Improvements in "cover" command
|
2014-07-25 12:04:40 +02:00 |
Clifford Wolf
|
6789e3002a
|
Removed Minisat dependency on zlib
|
2014-07-25 03:41:54 +02:00 |
Clifford Wolf
|
e4a0ab9bed
|
Added more stuff to the checklist
|
2014-07-25 03:41:53 +02:00 |
Clifford Wolf
|
7f1789ad1b
|
Fixed typo in cover id
|
2014-07-25 03:41:53 +02:00 |
Clifford Wolf
|
cd69925437
|
Added "make clean-abc"
|
2014-07-25 03:41:53 +02:00 |
Clifford Wolf
|
01dbf12ac9
|
Further improved "make" prettiness
|
2014-07-25 03:41:53 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
7a608437c6
|
Updated ABC to hg id "b1e63d18768d"
|
2014-07-24 20:57:21 +02:00 |
Clifford Wolf
|
9962384d3e
|
Added cover() calls to opt_const
|
2014-07-24 20:47:18 +02:00 |
Clifford Wolf
|
10d2402e2f
|
Added cover_list() API
|
2014-07-24 20:47:18 +02:00 |
Clifford Wolf
|
45b4154b37
|
Added "make SMALL=1"
|
2014-07-24 19:03:57 +02:00 |
Clifford Wolf
|
34ea9e3f09
|
Now "make PRETTY=1" is the default setting
|
2014-07-24 17:55:55 +02:00 |
Clifford Wolf
|
38afbe62ef
|
Added percentage display to "make PRETTY=1"
|
2014-07-24 17:53:11 +02:00 |
Clifford Wolf
|
b17d6531c8
|
Added "make PRETTY=1"
|
2014-07-24 17:15:01 +02:00 |
Clifford Wolf
|
2f54345cff
|
Added "cover" command
|
2014-07-24 16:14:19 +02:00 |