Eddie Hung
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5ebdc0f8e0
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Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
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2020-02-05 19:31:18 +01:00 |
Eddie Hung
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2245afa142
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More rigorous test
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2020-01-16 09:15:42 -08:00 |
Eddie Hung
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e30b6bbbf8
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
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2020-01-15 09:51:31 -08:00 |
Eddie Hung
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4a80510877
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Even more obvious testcase
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2019-12-11 23:52:05 -08:00 |
Eddie Hung
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61a1f3f49b
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Make testcase clearer with \o having its own init
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2019-12-11 23:48:09 -08:00 |
Eddie Hung
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e75ca29b19
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Add test: 'Warning: ignoring initial value on non-register: \o'
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2019-12-11 11:26:54 -08:00 |
Eddie Hung
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3fb604c75d
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Revert "Add test that is expecting to fail"
This reverts commit c28d4b8047 .
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2019-10-08 12:41:26 -07:00 |
Eddie Hung
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c28d4b8047
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Add test that is expecting to fail
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2019-10-02 14:52:40 -07:00 |
Eddie Hung
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00387f3927
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Revert to using clean
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2019-08-27 09:24:32 -07:00 |
Eddie Hung
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dc87372a97
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Wire with init on FF part, 1'bx on non-FF part
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2019-08-24 15:05:44 -07:00 |
Eddie Hung
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10c41a5cf5
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Blocking assignment
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2019-08-23 09:11:04 -07:00 |
Eddie Hung
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51ffb093b5
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In sat: 'x' in init attr should not override constant
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2019-08-22 16:43:08 -07:00 |
Zachary Snow
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5855024ccc
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support repeat loops with constant repeat counts outside of constant functions
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2019-04-09 12:28:32 -04:00 |
Clifford Wolf
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dbfd8460a9
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Allow $size and $bits in verilog mode, actually check test case
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2017-09-29 11:56:43 +02:00 |
Clifford Wolf
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8836943693
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Added yet another resource sharing test case
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2014-07-20 21:15:01 +02:00 |
Clifford Wolf
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3b52121d32
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now ignore init attributes on non-register wires in sat command
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2014-07-05 11:18:38 +02:00 |
Clifford Wolf
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482d9208aa
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Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
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2014-06-12 11:54:20 +02:00 |
Clifford Wolf
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039bb456cc
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Added test cases for expose -evert-dff
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2014-02-08 21:31:56 +01:00 |
Clifford Wolf
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244e8ce1f4
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Added splice command
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2014-02-07 20:30:56 +01:00 |
Clifford Wolf
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849fd62cfe
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Added counters sat test case
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2014-02-06 01:00:56 +01:00 |
Clifford Wolf
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7a66b38c3e
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Added test cases for sat command
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2014-02-04 13:43:34 +01:00 |