bbf343589b
Merge pull request #1998 from whitequark/cxxrtl-fixes
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cxxrtl: fix attribute syntax, minor fixes
2020-04-24 22:44:35 +00:00
a0e658d412
cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.`
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The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
2020-04-24 18:35:53 +00:00
3eb24809a1
Merge pull request #1995 from YosysHQ/eddie/fix_verific_wiretype
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verific: do not assert if wire not found; warn instead
2020-04-24 14:09:47 +02:00
4ca5f9799b
intel_alm: cleanup duplication
2020-04-24 11:26:48 +02:00
f88378ae61
cxxrtl: improve printing of narrow memories.
2020-04-24 05:50:36 +00:00
3738391bdd
cxxrtl: fix handling of parametric modules with large parameters.
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These have a `$paramod$` prefix, not `$paramod\\`.
2020-04-24 05:44:39 +00:00
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
b048afc3a6
Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs
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abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
2020-04-23 06:43:30 -07:00
dc9a72bc8d
Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs
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qbfsat: Make hole name recovery from source locations more robust.
2020-04-23 11:34:19 +02:00
1797c574da
Merge pull request #1988 from boqwxp/qbfsat
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qbfsat: Add `-assume-negative-polarity` option.
2020-04-23 11:33:54 +02:00
ca31027fe1
Merge pull request #1986 from YosysHQ/eddie/verific_enum
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verific: import enum attributes from verific
2020-04-23 11:28:05 +02:00
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
4ee8452d34
qbfsat: Make hole name recovery more robust. Allow multiple cell types to share the same source location as long as only one `$anyconst` or `$anyseq` has that location.
2020-04-23 05:45:44 +00:00
b700592881
Merge pull request #1984 from YosysHQ/eddie/getParam_exception
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kernel: Cell::getParam() to throw exception again if not found
2020-04-22 22:12:41 -07:00
7369e6b26b
qbfsat: Add `-assume-negative-polarity` option.
2020-04-23 04:06:15 +00:00
51ae0f4e20
ecp5: ecp5_gsr to skip cells that don't have GSR parameter again
2020-04-22 17:53:08 -07:00
988d47af85
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
592baebd22
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
2020-04-22 17:43:25 -07:00
5028e17f7d
verific: import enum attributes from verific
2020-04-22 17:26:56 -07:00
db09e96dff
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
d2d90e4504
xilinx: improve xilinx_dffopt message
2020-04-22 16:25:23 -07:00
f582eb14af
xilinx: xilinx_dffopt to read cells_sim.v; fix test
2020-04-22 16:25:23 -07:00
86ab7d3a6e
kernel: Cell::getParam() to throw exception again if not found
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As it did before #1945
2020-04-22 16:25:23 -07:00
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
274098cce6
Merge pull request #1983 from YosysHQ/eddie/use_default_param
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Cleanup use of hard-coded default parameters in light of #1945
2020-04-22 14:37:27 -07:00
cf14e186eb
Merge pull request #1982 from AsuMagic/asu/cxxrtl-memory-queue-opt
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cxxrtl: keep the memory write queue sorted on insertion.
2020-04-22 20:29:08 +00:00
beb9e4b299
Update passes/cmds/select.cc
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-22 21:31:32 +02:00
bf22cda912
Merge pull request #1969 from boqwxp/pool_emplace
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kernel: Add `pool` support for rvalue references and C++11 move semantics.
2020-04-22 12:10:42 -07:00
7f33a0294b
Cleanup use of hard-coded default parameters in light of #1945
2020-04-22 12:02:30 -07:00
dc77563a6a
cxxrtl: keep the memory write queue sorted on insertion.
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Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.
The Minerva SRAM SoC runs ~7% faster as a result.
2020-04-22 20:53:12 +02:00
db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966
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tests: fix various/plugin.sh when PREFIX != /usr/local/share
2020-04-22 10:19:30 -07:00
281cd10717
tests: update select black/white-box tests
2020-04-22 10:16:14 -07:00
eaa5a3e786
select: do not select black/white boxes by default, '=' prefix to do so
2020-04-22 10:15:56 -07:00
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
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design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
4f847cb64a
yosys-config: spelling
2020-04-22 08:30:03 -07:00
634b5e2d9f
tests: use `yosys-config --datdir` instead of hard-coded
2020-04-22 08:29:45 -07:00
a7c66fdc61
pool: add emplace() function
2020-04-22 08:14:07 -07:00
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
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sim: Fix handling of constant-connected cell inputs at startup
2020-04-22 16:57:34 +02:00
95c74b319b
Merge pull request #1979 from whitequark/cxxrtl-go-faster
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cxxrtl: Gas gas gas! I'm gonna step on the gas! Tonight I'll fly!
2020-04-22 16:50:45 +02:00
93288b8eae
cxxrtl: run edge detectors only once in eval().
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As a result, Minerva SRAM SoC runs ~15% faster.
2020-04-22 12:47:28 +00:00
1d5b6ac253
cxxrtl: add an unsupported knob for manipulating clock trees.
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This is quite possibly the worst way to implement this, but it does
work for a subset of well-behaved designs, and can be used to measure
how much performance is lost simulating the inactive edge of a clock.
It should be replaced with a clock tree analyzer generating safe
code once it is clear how should such a thing look like.
2020-04-22 01:15:27 +00:00
5f17e0ced5
cxxrtl: use log_id() where appropriate. NFC.
2020-04-21 23:42:56 +00:00
cd82afb740
bugpoint: Don't remove modules or cells while iterating over them.
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Reported by @ZirconiumX.
2020-04-22 00:09:01 +02:00
d22a8d157d
cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.
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If the annotations are not used, this commit does not alter semantics
at all, other than removing elision of outputs of black box cells.
(Elision of such outputs is expected to be too rare to have any
noticeable benefit, and the implementation was somewhat of a hack.)
The (* cxxrtl.comb *) annotation alters the semantics of the output
of the black box it is applied to such that, if the black box
converges immediately, no additional delta cycle is necessary to
propagate the computed combinatorial value upwards in hierarchy.
The (* cxxrtl.sync *) annotation alters the semantics of the output
of the black box it is applied to such as to remove any uses of
the black box by the wires connected to this output, and break false
feedback arcs arising from conservative modeling of dependencies of
the black box.
Although currently these attributes are only recognized on black
boxes, if separate compilation is added in the future, it could also
emit and consume them.
2020-04-21 22:08:36 +00:00
164b0746d2
cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.
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The attribute for this is called (* cxxrtl.edge *), and there is
a planned attribute (* cxxrtl.sync *) that would cause blackbox
cell outputs to be added to sync defs rather than comb defs.
Rename the edge detector related stuff to avoid confusion.
2020-04-21 18:46:36 +00:00
16a3048308
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
746c29b171
kernel: Rename arguments to rvalue-reference-accepting functions.
2020-04-21 17:17:47 +00:00
02f1c7b9af
write_json: dump default parameter values
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Fixes #1823 .
This will allow nextpnr to reuse the default value information already
present in yosys cells_sim.v and avoid duplicating (and probably
desyncing) this information.
2020-04-21 19:09:00 +02:00
b4d76309e1
Use default parameter value in getParam
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Fixes #1822 .
2020-04-21 19:09:00 +02:00
846c79b312
hierarchy: Convert positional parameters to named.
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Fixes #1821 .
2020-04-21 19:09:00 +02:00
whitequark
Claire Wolf
Dan Ravensloft
Eddie Hung
Alberto Gonzalez
Asu
Marcelina Kościelnicka