23b69ca32b
Improve read_verilog range out of bounds warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-20 23:48:53 +02:00
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
d9a4381012
Fixed memory leak
2018-10-20 11:57:39 +02:00
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error
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Fix issue #630
2018-10-17 12:13:18 +02:00
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
a36d1701dd
Fix build error with clang
2018-10-12 22:14:49 +02:00
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
cb214fc01d
Fix for issue 594.
2018-10-02 07:44:23 +00:00
62424ef3de
Add read_verilog $changed support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
9f9fe94b35
Fix handling of $past 2nd argument in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-30 18:43:35 +02:00
80a07652f2
Fixed issue #630 by fixing a minor typo in the previous commit
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(as well as a non critical minor code optimization)
2018-09-25 00:32:57 +03:00
c693f595c5
Merge branch 'master' into pr_reg_wire_error
2018-09-18 01:27:01 +03:00
f6fe73b31f
Fixed remaining cases where we check fo wire reg/wire incorrect assignments
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on Yosys-generated assignments.
In this case, offending code was:
module top(input in, output out);
function func;
input arg;
func = arg;
endfunction
assign out = func(in);
endmodule
2018-09-18 01:23:40 +03:00
042b3074f8
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
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This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
2018-08-23 15:26:02 +03:00
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error
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Fix remaining log_file_error(); emit dependent file references in new…
2018-08-15 14:01:34 +02:00
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
3101b9b8c9
Fix remaining log_file_error(); emit dependent file references in new line.
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There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
2018-07-20 18:52:52 -07:00
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
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Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
fe2ee833e1
Fix handling of signed memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 16:57:03 +02:00
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
4372cf690d
Add (* gclk *) attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
a572b49538
Replace -ignore_redef with -[no]overwrite
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
8364f509e3
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
bc80426d45
Remove some dead code
2017-10-10 12:00:48 +02:00
caa78388cd
Allow $past, $stable, $rose, $fell in $global_clock blocks
2017-10-10 11:59:32 +02:00
eb40278a16
Turned a few member functions into const, esp. dumpAst(), dumpVlog().
2017-09-30 07:37:38 +03:00
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
e951ac0dfb
$size() now works correctly for all cases!
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It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
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Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
7e391ba904
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
2017-09-26 09:19:56 +03:00
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
8f8baccfde
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
2017-06-07 12:30:24 +02:00
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
1e927a51d5
Preserve string parameters
2017-02-23 15:39:13 +01:00
4fb8007171
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
78f65f89ff
Fix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-15 13:52:50 +01:00
Clifford Wolf
Ruben Undheim
Tom Verbeure
Dan Gisselquist
Udi Finkelstein
Henner Zeller