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Fixed memory leak
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@ -1120,6 +1120,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
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// Generate RTLIL from AST for the new module and add to the design:
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AstModule *newmod = process_module(new_ast, false);
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delete(new_ast);
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design->add(newmod);
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RTLIL::Module* mod = design->module(original_name);
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if (is_top)
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