mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #673 from daveshah1/ecp5_improve
Small ECP5 improvements
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commit
11c8a9eb96
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@ -8,6 +8,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
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EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
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.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
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@ -265,16 +265,18 @@ module TRELLIS_IO(
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output O
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);
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parameter DIR = "INPUT";
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reg T_pd;
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always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
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generate
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if (DIR == "INPUT") begin
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assign B = 1'bz;
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assign O = B;
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end else if (DIR == "OUTPUT") begin
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assign B = T ? 1'bz : I;
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assign B = T_pd ? 1'bz : I;
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assign O = 1'bx;
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end else if (DIR == "INOUT") begin
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assign B = T ? 1'bz : I;
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end else if (DIR == "BIDIR") begin
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assign B = T_pd ? 1'bz : I;
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assign O = B;
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end else begin
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ERROR_UNKNOWN_IO_MODE error();
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@ -0,0 +1,11 @@
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module \$_DLATCH_N_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = !E ? D : Q;
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endmodule
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module \$_DLATCH_P_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = E ? D : Q;
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endmodule
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@ -266,10 +266,7 @@ struct SynthEcp5Pass : public ScriptPass
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if (abc2 || help_mode) {
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run("abc", " (only if -abc2)");
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}
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//TODO
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#if 0
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run("techmap -map +/ecp5/latches_map.v");
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#endif
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if (nomux)
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run("abc -lut 4");
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else
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