riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,619 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

175 Commits

Author SHA1 Message Date
Eddie Hung ca4f8c9444 xilinx: gate specify/attributes from iverilog 2020-05-14 10:33:57 -07:00
Eddie Hung a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung 4cec21b93e abc9_ops: -prep_dff_map to error if async flop found 2020-05-14 10:33:56 -07:00
Eddie Hung 6c66030dfb Uncomment negative setup times; clamp to zero for connectivity 2020-05-14 10:33:56 -07:00
Eddie Hung 95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Eddie Hung 7b543fdb0c xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
Eddie Hung f65fc845e5 xilinx: improve specify for DSP48E1 2020-03-04 11:31:12 -08:00
Eddie Hung 376319dc8d xilinx: Update RAMB* specify entries 2020-02-27 10:17:29 -08:00
Eddie Hung 3b74e0fa45 xilinx: add delays to INV 2020-02-27 10:17:29 -08:00
Eddie Hung b0ffd9cd8b Make +/xilinx/cells_sim.v legal 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung 7d86aceee3 Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy 2020-02-27 10:17:29 -08:00
Eddie Hung aac309626b Fix tests by gating some specify constructs from iverilog 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung 8408c13405 Update xilinx for ABC9 2020-02-27 10:17:29 -08:00
Eddie Hung ccc84f8923 Fix commented out specify statement 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00
Eddie Hung 0e7c55e2a7 Auto-generate .box/.lut files from specify blocks 2020-02-27 10:17:29 -08:00
Eddie Hung 5643c1b8c5 abc9_ops: -prep_lut and -write_lut to auto-generate LUT library 2020-02-27 10:17:29 -08:00
Eddie Hung 0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
Marcin Kościelnicki 7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Eddie Hung 0e4285ca0d abc9_ops: generate flop box ids, add abc9_required to FD* cells 2020-01-14 15:05:49 -08:00
Eddie Hung 28f814ee59 Add abc9_required to DSP48E1.{A,B,C,D,PCIN} 2020-01-10 17:12:31 -08:00
Eddie Hung 57f6826e29 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-08 18:30:20 -08:00
Eddie Hung 5c89dead5f Merge branch 'master' of github.com:YosysHQ/yosys 2020-01-06 16:51:32 -08:00
Eddie Hung 01866a7909 Fix DSP48E1 sim 2020-01-06 16:45:29 -08:00
Eddie Hung 98ee8c14df Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
Eddie Hung 28bf712372 Wrap arrival functions inside `YOSYS too 2020-01-06 11:55:56 -08:00
Eddie Hung 27c150bfcc Fix return value of arrival time functions, fix word 2020-01-06 11:39:08 -08:00
Eddie Hung 020606f81c Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required 2020-01-06 09:44:00 -08:00
Eddie Hung 3012e9eebc Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor 2020-01-02 12:48:07 -08:00
Eddie Hung b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung d0d3ab8f67 ifndef __ICARUS__ -> ifdef YOSYS 2020-01-01 17:33:47 -08:00
Eddie Hung 3d98a96273 ifdef __ICARUS__ -> ifndef YOSYS 2020-01-01 17:33:10 -08:00
Eddie Hung db04161eca Rework abc9's DSP48E1 model 2020-01-01 17:30:26 -08:00
Eddie Hung 44d9fb0e7c Re-arrange FD order 2019-12-31 18:47:38 -08:00
Eddie Hung 4cdba00e25 FDCE ports to be alphabetical 2019-12-31 15:24:02 -08:00
Eddie Hung 543bd2de6c Update timings for Xilinx S7 cells 2019-12-30 14:36:07 -08:00
Eddie Hung 405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Eddie Hung 4eaa45091c Update some abc9_arrival times, add abc9_required times 2019-12-27 14:47:50 -08:00
Marcin Kościelnicki dadaf7ed78 xilinx: Test our DSP48A/DSP48A1 simulation models. 2019-12-23 20:36:43 +01:00
Eddie Hung d3fc94405f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 14:07:23 -08:00
Eddie Hung 5986a4df40 Add abc9_arrival times for RAM{32,64}M 2019-12-20 14:06:59 -08:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Marcin Kościelnicki 8b2c9f4518 xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00