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12641 Commits

Author SHA1 Message Date
Lofty a79b15e947
Merge pull request #3992 from YosysHQ/empty-case-fix 
write_verilog: avoid emitting empty cases.
 2023-10-08 08:05:10 +01:00
Wanda c36cf9c5ac write_verilog: avoid emitting empty cases. 
The Verilog grammar does not allow an empty case.  Most synthesis tools
are quite permissive about this, but Quartus is not.  This causes
problems for amaranth with Quartus (see amaranth-lang/amaranth#931).
 2023-10-08 01:11:30 +02:00
Lofty a1923a5f77
Merge pull request #3988 from YosysHQ/micko/fix_leak 
Fix readline/editline memory leak
 2023-10-07 20:50:01 +01:00
github-actions[bot] 51e9b0882b Bump version 2023-10-07 00:14:44 +00:00
Miodrag Milanovic 2ab7d1d0c8 Fix readline/editline memory leak 2023-10-06 16:05:44 +02:00
Martin Povišer 8367f06188 ast/simplify: Remove unused in_param code 2023-10-05 22:42:36 -04:00
github-actions[bot] fc815fdb47 Bump version 2023-10-06 00:14:52 +00:00
Miodrag Milanović a54e6f2d1f
Merge pull request #3984 from YosysHQ/module_hdlname 
verific: save original module name
 2023-10-05 19:41:00 +02:00
Jannis Harder 6b8203f8a0
Merge pull request #3985 from jix/static-elaboration-top 2023-10-05 17:45:36 +02:00
Jannis Harder 47a4b790f8 verific: Pass top modules to static elaboration when using hierarchy 2023-10-05 16:51:49 +02:00
Jannis Harder 23b9e61c47 verific: Pass list of top modules to static elaboration 2023-10-05 16:51:49 +02:00
Miodrag Milanovic 268fe92d22 verific: save original module name 2023-10-05 11:22:40 +02:00
Miodrag Milanovic 824fdaadf6 mingw build fix 2023-10-05 09:55:53 +02:00
Miodrag Milanovic b88f7fc6e8 Next dev cycle 2023-10-05 09:16:05 +02:00
Miodrag Milanovic 4a1b559925 Release version 0.34 2023-10-05 09:14:12 +02:00
Miodrag Milanović 881ce80a11
Merge pull request #3982 from povik/booth-fix 
booth: Fix vacancy check when summing down result
 2023-10-05 08:15:45 +02:00
Martin Povišer 4506e11d0f booth: Extend test to catch bug from previous commit 2023-10-04 23:30:29 +02:00
Martin Povišer 0434f9d3d1 booth: Fix vacancy check when summing down result 
In commit fedd12261 ("booth: Move away from explicit `Wire` pointers")
a bug was introduced when checking for vacant slots in arrays holding
some intermediate results. Non-wire SigBit values were taken to imply
a vacant slot, but actually a constant one can make its way into those
results, if the multiplier cell configuration is just right. Fix the
vacancy check to address the bug.
 2023-10-04 23:21:40 +02:00
Lofty 3e02b63ee1
Merge pull request #3977 from YosysHQ/lofty/gowin-dff 
gowin: fix abc9 attributes and specify blocks
 2023-10-04 05:18:59 +01:00
github-actions[bot] f00d6f3c12 Bump version 2023-10-04 00:15:12 +00:00
Lofty 294844137b gowin: fix abc9 attributes and specify blocks 2023-10-04 00:16:10 +01:00
Jannis Harder aeb742b8b3
Merge pull request #3979 from jix/verific-L-handling 2023-10-03 16:43:52 +02:00
Jannis Harder 563a56d9ff verific: Improve interaction between -L, -work and bind statements 2023-10-03 15:52:01 +02:00
Miodrag Milanović 493685b7d2
Merge pull request #3978 from jix/fix-sva-test 
Fix sva_value_change_changed test for updated verific
 2023-10-03 12:19:10 +02:00
Jannis Harder c174597014 Fix sva_value_change_changed test for updated verific 2023-10-03 11:46:43 +02:00
Rasmus Munk Larsen a6247cba42 Fix compiler warnings from GCC. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen cb9f318d37 Remove local modifications. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen ff915d21b6 Update comment. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen 4968229efc Speed up stringf / vstringf by 1.8x. 
The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement.
 2023-10-03 09:29:06 +01:00
github-actions[bot] 11ffd7df40 Bump version 2023-10-03 00:15:18 +00:00
Rasmus Munk Larsen 1bbc12f389 Revert changes to techmap.cc. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen 67f1700486 Revert formatting changes. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen abd9c51963 Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen 98d2c9088a Ignore emacs auto-save files. 2023-10-02 17:26:37 +01:00
Jannis Harder 8b42abee50
Merge pull request #3961 from jix/dft-fixes 2023-10-02 16:58:15 +02:00
Jannis Harder ecf09b9271
Merge pull request #3962 from jix/sim-noinitstate 2023-10-02 16:57:46 +02:00
Martin Povišer b894abf8b1
Merge pull request #3959 from rmlarsen/decode_string 
Speed up RTLIL::Const::decode_string by 1.7x.
 2023-10-02 16:38:43 +02:00
N. Engelhardt dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
github-actions[bot] b52f6cb199 Bump version 2023-09-30 00:14:39 +00:00
Jannis Harder 7aa26b3a0b
Merge pull request #3966 from jix/fix-nullptr-fixup-hierarchy-flags 2023-09-29 13:24:31 +02:00
Jannis Harder cc843d414f simplify: Avoid calling fixup_hierarchy_flags on nullptr 
Compiling on GCC hid this bug as it optimized the nullptr call away as
undefined behavior, but running the SBY tests with a clang build hits
this error.
 2023-09-29 12:28:50 +02:00
Rasmus Munk Larsen 12218a4c74 Unflip i and j. 2023-09-28 19:39:09 -07:00
Jannis Harder 5daa49bafb dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not 2023-09-28 17:33:55 +02:00
Jannis Harder 7eaa4bcb46 sim: Add -noinitstate option and handle non-cosim initstate 
This adds the -noinitstate option which is required to simulate
counterexamples to induction with yw-cosim. Also add handling for
$initstate cells for non-co-simulation.
 2023-09-28 17:29:24 +02:00
Martin Povišer 20024900d9
Merge pull request #3813 from povik/ast-simplify-work-vol2 
ast/simplify: Remove in_lvalue/in_param simplify() parameters
 2023-09-28 11:57:58 +02:00
Martin Povišer b0045300fd booth: Cut down the test 
Cut the test down from taking ~25 s to ~3 s.
 2023-09-28 11:55:51 +02:00
Martin Povišer 6b70b3dbef booth: Fix assertion 
Fix assertion to what it should be per Andy's comments.
 2023-09-28 11:50:57 +02:00
Rasmus Munk Larsen 01a015747e Speed up RTLIL::Const::decode_string by 1.7x. 2023-09-27 17:16:13 -07:00
github-actions[bot] ac8b31e000 Bump version 2023-09-28 00:15:01 +00:00
Miodrag Milanović b35ea8f896
Merge pull request #3957 from YosysHQ/ver_def_param 
Verific: add default parameters to modules
 2023-09-27 17:37:58 +02:00