mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3979 from jix/verific-L-handling
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commit
aeb742b8b3
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@ -3063,6 +3063,7 @@ struct VerificPass : public Pass {
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int argidx = 1;
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std::string work = "work";
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bool is_work_set = false;
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(void)is_work_set;
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veri_file::RegisterCallBackVerificStream(&verific_read_cb);
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if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
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@ -3140,7 +3141,20 @@ struct VerificPass : public Pass {
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}
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veri_file::RemoveAllLOptions();
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veri_file::AddLOption("work");
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for (int i = argidx; i < GetSize(args); i++)
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{
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if (args[i] == "-work" && i+1 < GetSize(args)) {
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work = args[++i];
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is_work_set = true;
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continue;
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}
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if (args[i] == "-L" && i+1 < GetSize(args)) {
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++i;
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continue;
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}
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break;
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}
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veri_file::AddLOption(work.c_str());
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for (int i = argidx; i < GetSize(args); i++)
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{
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if (args[i] == "-work" && i+1 < GetSize(args)) {
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@ -3148,7 +3162,7 @@ struct VerificPass : public Pass {
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continue;
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}
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if (args[i] == "-L" && i+1 < GetSize(args)) {
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if (args[++i] == "work")
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if (args[++i] == work)
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veri_file::RemoveAllLOptions();
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continue;
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}
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@ -3641,7 +3655,7 @@ struct VerificPass : public Pass {
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if (module_name && module_name->IsHierName()) {
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VeriName *prefix = module_name->GetPrefix() ;
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const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
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if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
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if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
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}
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if (lib && module_name)
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top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
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@ -3663,13 +3677,19 @@ struct VerificPass : public Pass {
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log_error("Can't find module/unit '%s'.\n", name);
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}
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if (veri_lib) {
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// Also elaborate all root modules since they may contain bind statements
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MapIter mi;
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VeriModule *veri_module;
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FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
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if (!veri_module->IsRootModule()) continue;
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veri_modules.InsertLast(veri_module);
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const char *lib_name = nullptr;
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SetIter si;
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FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
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VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
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if (veri_lib) {
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// Also elaborate all root modules since they may contain bind statements
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MapIter mi;
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VeriModule *veri_module;
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FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
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if (!veri_module->IsRootModule()) continue;
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veri_modules.InsertLast(veri_module);
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}
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}
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}
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