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Merge pull request #3957 from YosysHQ/ver_def_param
Verific: add default parameters to modules
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commit
b35ea8f896
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@ -1275,9 +1275,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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log("Importing module %s.\n", RTLIL::id2cstr(module->name));
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}
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import_attributes(module->attributes, nl, nl);
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const char *param_name ;
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const char *param_value ;
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MapIter mi;
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FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
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module->avail_parameters(RTLIL::escape_id(param_name));
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module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value);
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}
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SetIter si;
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MapIter mi, mi2;
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MapIter mi2;
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Port *port;
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PortBus *portbus;
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Net *net;
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