Eddie Hung
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5e487b103c
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Fix submod -hidden
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2019-11-26 23:26:25 -08:00 |
Eddie Hung
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435d33c373
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Add -hidden option to submod
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2019-11-26 23:26:12 -08:00 |
Eddie Hung
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de3476cc23
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No need for -abc9
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2019-11-26 23:08:14 -08:00 |
Marcin Kościelnicki
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fdcbda195b
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opt_share: Fix handling of fine cells.
Fixes #1525.
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2019-11-27 08:01:07 +01:00 |
Eddie Hung
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5e67df38ed
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latch -> box
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2019-11-26 22:59:05 -08:00 |
Eddie Hung
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f1538c3642
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Merge branch 'master' into xaig_dff
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2019-11-26 22:56:53 -08:00 |
Eddie Hung
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4a0198128e
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Add citation
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2019-11-26 22:51:16 -08:00 |
Eddie Hung
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2105ae176a
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Check for either sign or zero extension for postAdd packing
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2019-11-26 22:51:00 -08:00 |
Eddie Hung
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15042eaf57
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Remove notes
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2019-11-26 22:41:35 -08:00 |
Eddie Hung
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a30d5e1cc3
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Fold loop
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2019-11-26 21:57:50 -08:00 |
Eddie Hung
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68717dd03b
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Do not sigmap keep bits inside write_xaiger
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2019-11-26 21:57:50 -08:00 |
Eddie Hung
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7136cee6b4
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xaiger: do not promote output wires
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2019-11-26 21:55:37 -08:00 |
Eddie Hung
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222e199b73
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Add testcase derived from fastfir_dynamictaps benchmark
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2019-11-26 21:26:30 -08:00 |
Eddie Hung
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99702efaba
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xaiger: do not promote output wires
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2019-11-26 19:03:02 -08:00 |
Eddie Hung
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739f530906
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Move 'clean' from map_luts to finalize
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2019-11-26 14:51:39 -08:00 |
Eddie Hung
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09637dd3e4
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Fix submod -hidden
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2019-11-26 11:57:26 -08:00 |
Eddie Hung
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3027f015c2
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clkpart to use 'submod -hidden'
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2019-11-26 11:35:32 -08:00 |
Eddie Hung
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e8aa92ca35
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Add -hidden option to submod
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2019-11-26 11:35:15 -08:00 |
Eddie Hung
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eb666b4677
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Update docs with bullet points
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2019-11-26 11:12:58 -08:00 |
Marcin Kościelnicki
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0466c48533
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xilinx: Add simulation models for IOBUF and OBUFT.
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2019-11-26 08:15:20 +01:00 |
Eddie Hung
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0d7ba77426
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Move \init from source wire to submod if output port
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2019-11-25 16:07:47 -08:00 |
Eddie Hung
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dd317c9280
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Add testcase where \init is copied
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2019-11-25 16:07:35 -08:00 |
Eddie Hung
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da51492dbc
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Fold loop
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2019-11-25 15:43:37 -08:00 |
Eddie Hung
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7f0914a408
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Do not sigmap keep bits inside write_xaiger
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2019-11-25 15:42:07 -08:00 |
Eddie Hung
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67be62a957
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clkpart to analyse async flops too
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2019-11-25 13:39:37 -08:00 |
Eddie Hung
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6831510f5b
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Fix debug
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2019-11-25 12:59:34 -08:00 |
Eddie Hung
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d087024caf
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-25 12:42:09 -08:00 |
Eddie Hung
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6a2eb5d8f9
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Special abc9_clock wire to contain only clock signal
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2019-11-25 12:36:13 -08:00 |
Eddie Hung
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180cb39395
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abc9 to contain time call
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2019-11-25 12:35:57 -08:00 |
Eddie Hung
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f50b6422b0
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abc9 to no longer to clock partitioning, operate on whole modules only
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2019-11-25 12:35:38 -08:00 |
Eddie Hung
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63b7a48fbc
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clkpart to analyse async flops too
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2019-11-25 12:04:11 -08:00 |
Marcin Kościelnicki
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6cdea425b8
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clkbufmap: Add support for inverters in clock path.
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2019-11-25 20:40:39 +01:00 |
Marcin Kościelnicki
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7562e7304e
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xilinx: Use INV instead of LUT1 when applicable
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2019-11-25 20:40:39 +01:00 |
Pepijn de Vos
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72d03dc910
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attempt to fix formatting
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2019-11-25 14:50:34 +01:00 |
Pepijn de Vos
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6c79abbf5a
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gowin: add and test dff init values
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2019-11-25 14:33:21 +01:00 |
Eddie Hung
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23ecf12bbf
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
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2019-11-23 10:29:03 -08:00 |
Eddie Hung
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15aa3f460d
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More oopsies
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2019-11-23 10:28:46 -08:00 |
Eddie Hung
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bf1167bc64
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Conditioning abc9 on POs not accurate due to cells
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2019-11-23 10:26:55 -08:00 |
Eddie Hung
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eb11c06a69
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For abc9, run clkpart before ff_map and after abc9
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2019-11-23 10:18:22 -08:00 |
Eddie Hung
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7b2bccb3d3
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
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2019-11-23 10:18:06 -08:00 |
Eddie Hung
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722eeacc09
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Print ".en=" only if there is an enable signal
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2019-11-23 10:17:31 -08:00 |
Eddie Hung
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907c8aeaef
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Escape IdStrings
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2019-11-23 10:16:56 -08:00 |
Eddie Hung
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165f5cb6cf
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More sane naming of submod
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2019-11-23 10:01:09 -08:00 |
Eddie Hung
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66ff0511a0
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Add -set_attr option, -unpart to take attr name
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2019-11-23 09:52:17 -08:00 |
Eddie Hung
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fb49da21bd
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
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2019-11-23 08:39:19 -08:00 |
Eddie Hung
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b46e636c91
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Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
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2019-11-23 08:38:48 -08:00 |
Eddie Hung
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23fcdd96b3
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Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
xaig_dff to support async flops $_DFF_[NP][NP][01]_
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2019-11-23 08:22:03 -08:00 |
Eddie Hung
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96941aacbb
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Do not use log_signal() for empty SigSpec to prevent "{ }"
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2019-11-22 23:29:10 -08:00 |
Eddie Hung
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736b96b186
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Call submod once, more meaningful submod names, ignore largest domain
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2019-11-22 23:16:15 -08:00 |
Eddie Hung
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1851f4b488
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
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2019-11-22 23:01:18 -08:00 |