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8351 Commits

Author SHA1 Message Date
David Shah 82a2972068 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 16:45:51 +01:00
David Shah 482926cbd3 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 15:53:21 +01:00
David Shah 92694ea3a9 verilog_lexer: Increase YY_BUF_SIZE to 65536 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 13:35:39 +01:00
Bogdan Vukobratovic 07c4a7d438 Implement opt_share 
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
 2019-07-26 11:36:48 +02:00
David Shah da6701c4cd Fix frontend auto-detection for gzipped input 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:29:05 +01:00
David Shah 933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Eddie Hung a02d1720a7 Merge branch 'master' of github.com:YosysHQ/yosys 2019-07-25 10:49:26 -07:00
Eddie Hung c5e31ac9c3 Bump abc to fix &mfs bug 2019-07-25 10:48:58 -07:00
Eddie Hung 297a980212 Bump abc to fix &mfs bug 2019-07-25 10:44:20 -07:00
Clifford Wolf eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Clifford Wolf 5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Clifford Wolf 2bdd8003d3
Merge pull request #1219 from jakobwenzel/objIterator 
made ObjectIterator comply with Iterator Interface
 2019-07-25 17:19:11 +02:00
Eddie Hung 5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
Jakob Wenzel 70882a8070 replaced std::iterator with using statements 2019-07-25 09:51:09 +02:00
David Shah ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Jim Lawson 7e298084e4 Call log_error() instead of log_warning() on unsupported cell type in FIRRTL backend. 2019-07-24 13:33:16 -07:00
Eddie Hung d6a289d3e3
Merge pull request #1222 from koriakin/s6-example 
Add a simple example for Spartan 6
 2019-07-24 10:51:03 -07:00
Eddie Hung c39ccc65e9 Add copyright header, comment on cascade 2019-07-24 10:49:09 -07:00
Jim Lawson c66b7402c0 Merge remote-tracking branch 'upstream/master' 2019-07-24 10:20:46 -07:00
Marcin Kościelnicki 173c975894 Add a simple example for Spartan 6 2019-07-24 18:59:03 +02:00
Jakob Wenzel 25685a9a5b made ObjectIterator extend std::iterator 
this makes it possible to use std algorithms on them
 2019-07-24 16:35:40 +02:00
Dan Ravensloft 49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Eddie Hung 79fd6edc5a Eliminate warnings by sizing O correctly 2019-07-23 15:13:30 -07:00
Eddie Hung 151c5c96c0 Typo for Y_WIDTH 2019-07-23 15:05:20 -07:00
Eddie Hung a37574ccbf Fix muxAB logic 2019-07-23 14:52:14 -07:00
Eddie Hung 0dd2a125f6 Remove debug print 2019-07-23 14:21:45 -07:00
Eddie Hung dc0c853abe Simplify and fix for MACs 2019-07-23 14:20:34 -07:00
Eddie Hung 4f11ff8ebd Fix typo 2019-07-23 13:58:56 -07:00
Dan Ravensloft 67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Eddie Hung a66f17b6a7
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp 
ice40: Fix SB_MAC16 sim model for signed modes
 2019-07-23 09:56:58 -07:00
Eddie Hung 33c984a044 Fix spacing 2019-07-22 16:37:13 -07:00
Eddie Hung cb505c50d3 Remove debug 2019-07-22 16:14:15 -07:00
Eddie Hung 068617f094 Pack hi and lo registers separately 2019-07-22 16:12:57 -07:00
Eddie Hung 8c31441ba0 SigSpec::extract() to return as many bits as poss if out of bounds 2019-07-22 16:10:21 -07:00
Eddie Hung 4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung 304cefbbe2 Pack Y register 2019-07-22 15:05:16 -07:00
Eddie Hung 5e70b8a22b opt and wreduce necessary for -dsp 2019-07-22 13:48:33 -07:00
Eddie Hung 5a14b6e1f6 Pack adders not just accumulators 2019-07-22 13:01:49 -07:00
Eddie Hung 3a7aeb028d Use minimum sized width wires 2019-07-22 13:01:26 -07:00
Eddie Hung 280288a62a Update changelog 2019-07-22 07:46:06 -07:00
Eddie Hung be3d9c8eaa
Merge pull request #1214 from jakobwenzel/astmod_clone 
initialize noblackbox and nowb in AstModule::clone
 2019-07-22 07:42:53 -07:00
Jakob Wenzel e2fe8e0a4f initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
Clifford Wolf c6d8692c97 Add "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-20 15:06:28 +02:00
Eddie Hung e0720a8018 Restore old ffY behaviour 2019-07-19 22:47:08 -07:00
Eddie Hung f9d08a5e5e Cleanup 2019-07-19 20:25:28 -07:00
Eddie Hung 47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung 595a8f032f Do not do sign extension in techmap; let packer do it 2019-07-19 15:50:13 -07:00
Eddie Hung 09beeee38a Try and fix again 2019-07-19 14:40:57 -07:00
Eddie Hung e87916b7eb Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp 2019-07-19 14:03:34 -07:00
Eddie Hung c926eeb43a Add another test 2019-07-19 14:02:46 -07:00