68 Commits

Author	SHA1	Message	Date
David Shah	c4bfbecca6	Update .gitignore ... Signed-off-by: David Shah <dave@ds0.me>	2020-10-01 15:53:14 +01:00
N. Engelhardt	dc4a617694	add tests	2020-09-28 18:16:08 +02:00
Xiretza	acd47bbd52	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
Eddie Hung	46ed0db2ec	Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings ... tests: reduce test warnings	2020-06-03 08:37:07 -07:00
Eddie Hung	60aa804915	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
Eddie Hung	95dcd7e785	test: add attribute-before-stmt test from @nakengelhardt	2020-05-25 07:36:53 -07:00
Eddie Hung	1c117ac023	verilog: do not warn for attributes on null statements	2020-05-25 07:36:53 -07:00
Eddie Hung	29d84339bf	tests: add an generate-else test too	2020-05-25 07:36:53 -07:00
Eddie Hung	589775538c	tests: add #2037 testcase	2020-05-25 07:36:53 -07:00
Eddie Hung	574812d9a5	Merge pull request #2057 from YosysHQ/eddie/fix_task_attr ... verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)	2020-05-21 11:00:36 -07:00
Eddie Hung	e7fd8912f0	tests: attributes before task enable	2020-05-14 16:09:41 -07:00
Eddie Hung	5bcde7ccc3	Merge pull request #2045 from YosysHQ/eddie/fix2042 ... verilog: error if no direction given for task arguments, default to input in SV mode	2020-05-14 09:45:54 -07:00
Eddie Hung	56a5b1d2da	test: add another testcase as per @nakengelhardt	2020-05-14 08:36:36 -07:00
Eddie Hung	0d2c33f9f4	tests: update/extend task argument tests	2020-05-13 10:11:45 -07:00
Eddie Hung	e5ce5a4fd5	tests: add #2042 testcase	2020-05-11 11:05:19 -07:00
Eddie Hung	b11cf67a81	Setup tests/verilog properly	2020-05-11 10:31:02 -07:00
Eddie Hung	004999218f	techlibs/common: more robustness when *_WIDTH = 0	2020-05-05 08:01:27 -07:00
Eddie Hung	2e911bc806	test: add failing test	2020-05-04 12:18:02 -07:00