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11529 Commits

Author SHA1 Message Date
Alberto Gonzalez 76dfa81790
cutpoint: Improve efficiency by iterating over module ports instead of module wires. 2020-06-18 17:42:36 +00:00
N. Engelhardt dfde1cf1c5
Merge pull request #2153 from boqwxp/splitnets-cleanup 
splitnets: Cleanup and efficiency improvements
 2020-06-18 19:16:55 +02:00
whitequark 8344846787
Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug 
cxxrtl: don't compute vital values in log_assert()
 2020-06-18 16:57:51 +00:00
whitequark 5439faebf9
Merge pull request #2142 from whitequark/splitnets-hdlname 
splitnets: propagate (*hdlname*) and disambiguate via start_offset
 2020-06-18 16:57:24 +00:00
Miodrag Milanović 2123019ac6
Merge pull request #2164 from madebr/msvc 
Get yosys building on Visual Studio
 2020-06-18 12:44:21 +02:00
whitequark 3c4e974d7b cxxrtl: don't compute vital values in log_assert(). 
This breaks NDEBUG builds.

Fixes #2166.
 2020-06-17 19:27:47 +00:00
Anonymous Maarten 60fb9cabcf msvc does not support designated initializers in structs 2020-06-17 16:20:52 +02:00
Anonymous Maarten 504f220619 MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
Anonymous Maarten 35008e6d40 MSVC cannot omit operand in conditional 2020-06-17 15:10:08 +02:00
Anonymous Maarten c9c13c29df MSVC defines TRANSPARENT too 2020-06-17 15:10:08 +02:00
whitequark c4f20f744b
Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo 
cxxrtl: restrict the debug info of a blackbox to its ports.
 2020-06-17 06:07:41 +00:00
whitequark eaf66037a5
Merge pull request #2160 from whitequark/cxxrtl-fix-warning 
cxxrtl: avoid unused variable warning for transparent $memrd ports
 2020-06-17 06:06:58 +00:00
Jean-François Nguyen 8d98c3861d cxxrtl: restrict the debug info of a blackbox to its ports. 2020-06-16 15:30:56 +02:00
N. Engelhardt 39ba90a8b8
Merge pull request #2156 from XarkLabs/master 
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
 2020-06-16 12:31:34 +02:00
whitequark 334ec5fa0a
Merge pull request #2159 from MerryMage/cxxrtl-mul 
cxxrtl: Implement chunk-wise multiplication
 2020-06-15 06:08:17 +00:00
whitequark 8d70f7abf9 cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC. 2020-06-15 06:00:16 +00:00
MerryMage f7ae9b0851 cxxrtl: Implement chunk-wise multiplication 2020-06-15 05:54:57 +01:00
whitequark 9d0f1aa222
Merge pull request #2158 from miek/sshr-sign-extension 
cxxrtl: fix sshr sign-extension.
 2020-06-15 01:37:05 +00:00
Mike Walters 66a2de2912 cxxrtl: fix sshr sign-extension. 2020-06-15 01:01:49 +01:00
Xark 9509444ef2 Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
whitequark 74e93e083f
Merge pull request #2155 from whitequark/fix-wasm-wasi-sdk-11 
kernel: guard include of signal.h more precisely
 2020-06-13 23:28:18 +00:00
whitequark 7137f99658 kernel: guard include of signal.h more precisely. 
Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
 2020-06-13 22:37:04 +00:00
whitequark 971a765155
Merge pull request #2151 from whitequark/cxxrtl-fix-rzext 
cxxrtl: fix rzext()
 2020-06-13 22:18:35 +00:00
Alberto Gonzalez f5d7cd60f5
splitnets: Clean up pseudo-private member usage 2020-06-13 05:47:55 +00:00
Alberto Gonzalez b70de98bd1
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups 2020-06-13 05:26:30 +00:00
whitequark dc6961f3d4
Merge pull request #2145 from whitequark/cxxrtl-splitnets 
cxxrtl: handle multipart signals
 2020-06-13 04:23:22 +00:00
whitequark 3783ad625e
Merge pull request #2152 from whitequark/cxxrtl-always-inline 
cxxrtl: always inline internal cells and slice/concat operations
 2020-06-13 04:17:49 +00:00
whitequark 107911dbec cxxrtl: always inline internal cells and slice/concat operations. 
This can result in massive reduction in runtime, up to 50% depending
on workload. Currently people are using `-mllvm -inline-threshold=`
as a workaround (with clang++), but this solution is more portable.
 2020-06-13 01:52:06 +00:00
whitequark 6cf02ed94f cxxrtl: fix rzext(). 
This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.
 2020-06-13 00:49:44 +00:00
whitequark a5f0cb4eba
Merge pull request #2150 from whitequark/cxxrtl-elide-pmux 
cxxrtl: elide $pmux cells
 2020-06-12 08:50:57 +00:00
whitequark b793e4753b cxxrtl: elide $pmux cells. 
On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.
 2020-06-12 02:40:30 +00:00
whitequark a1785e988b
Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputs 
cxxrtl: unbuffer output wires of toplevel module
 2020-06-12 01:59:35 +00:00
whitequark d5ecd4a570 cxxrtl: annotate port direction as comments. 2020-06-12 00:35:18 +00:00
whitequark 29bd81d662 cxxrtl: unbuffer output wires of toplevel module. 
Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.

This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
 2020-06-12 00:31:57 +00:00
whitequark cd7bf115b6 cxxrtl: simplify unbuffering of input wires. 
This also fixes an edge case with (*keep*) input ports.
 2020-06-12 00:31:57 +00:00
whitequark 8d712b1095 cxxrtl: handle multipart signals. 
This avoids losing design visibility when using the `splitnets` pass.
 2020-06-11 19:34:35 +00:00
Dan Ravensloft 8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
whitequark fa04b19670 cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. 2020-06-11 12:43:17 +00:00
whitequark 2139a5c21a splitnets: propagate (*hdlname*) and disambiguate via start_offset. 
This allows reliably coalescing the split wires later.
 2020-06-10 19:59:08 +00:00
whitequark 8a4841d786
Merge pull request #2141 from whitequark/cxxrtl-cxx11 
cxxrtl: various compiler compatibility fixes
 2020-06-10 17:10:15 +00:00
whitequark 072b14f1a9
Merge pull request #2140 from whitequark/cxxrtl-aliases 
cxxrtl: disambiguate values/wires and their aliases in debug info
 2020-06-10 16:09:27 +00:00
whitequark 6021ff727d cxxrtl: restore C++11 compatibility. 
This is necessary to be able to build CXXRTL models via yosys-config.
 2020-06-10 15:57:07 +00:00
whitequark cde99e696a cxxrtl: fix a few gcc warnings. 2020-06-10 15:57:07 +00:00
whitequark 574f5cb5b2 Fix formatting. NFC. 2020-06-10 15:48:40 +00:00
diego d68a8f9e2b Removing trailing whitespace 2020-06-10 10:35:40 -05:00
whitequark 0955a603c8 cxxrtl: disambiguate values/wires and their aliases in debug info. 
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
 2020-06-10 14:39:45 +00:00
whitequark 8f1a320646
Merge pull request #2134 from whitequark/cxxrtl-opt-debug 
cxxrtl: introduce -Og optimization level
 2020-06-10 11:51:04 +00:00
clairexen b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs 
Do not optimize away FFs in "prep" and Verific front-end
 2020-06-10 12:44:23 +02:00
clairexen a408771c62
Merge pull request #2139 from YosysHQ/verific_missing_memory 
verific - detect missing memory to prevent crash.
 2020-06-10 12:42:43 +02:00
Miodrag Milanovic d6bec3ba1c verific - detect missing memory to prevent crash. 2020-06-10 11:27:44 +02:00