riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,507 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

1507 Commits

Author SHA1 Message Date
Clifford Wolf 9bacc0b54c Added stackmap<> container 2014-08-17 00:56:47 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf f82c978e08 Fixed AOI/OAI expr handling in verilog backend 2014-08-16 22:05:09 +02:00
Clifford Wolf 976bda7102 Multiply using a carry-save accumulator 2014-08-16 21:07:29 +02:00
Clifford Wolf 3b9157f9a6 Added "test_cell -s <seed>" 2014-08-16 19:44:31 +02:00
Clifford Wolf 83e2698e10 AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map 2014-08-16 19:31:59 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf 56a30cf42c Added CellTypes::cell_evaluable() 2014-08-16 16:17:07 +02:00
Clifford Wolf 1ddf150c35 Changes in techmap $__alu interface 2014-08-16 16:01:58 +02:00
Clifford Wolf eb17fbade5 Added "opt -fast" 2014-08-16 15:34:15 +02:00
Clifford Wolf dbdf89c705 Added log_spacer() 2014-08-16 15:34:00 +02:00
Clifford Wolf 674f421b47 Bugfix in iopadmap 2014-08-15 14:29:42 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf bf486002d9 Removed old doc references to $safe_pmux 2014-08-15 14:04:35 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf 8ff71b5ae5 Added Frontend "+/" filename syntax for files from proc_share_dir 2014-08-15 02:08:02 +02:00
Clifford Wolf d320e75087 document "techmap -map %<design-name>" 2014-08-15 02:01:30 +02:00
Clifford Wolf c7afbd9d8e Fixed bug in "read_verilog -ignore_redef" 2014-08-15 01:53:22 +02:00
Clifford Wolf 978a933b6a Added RTLIL::SigSpec::to_sigbit_map() 2014-08-14 23:14:47 +02:00
Clifford Wolf c83b990458 Changed the AST genWidthRTLIL subst interface to use a std::map 2014-08-14 23:02:07 +02:00
Clifford Wolf 2f44d8ccf8 Added sig.{replace,remove,extract} variants for std::{map,set} pattern 2014-08-14 22:32:18 +02:00
Clifford Wolf 6d56172c0d Fixed line numbers when using here-doc macros 2014-08-14 22:26:30 +02:00
Clifford Wolf 85e3cc12ac Fixed handling of task outputs 2014-08-14 22:26:10 +02:00
Clifford Wolf 5602cbde9f Simplified $__arraymul techmap rule 2014-08-14 20:53:21 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 28cf48e31f Some improvements in FSM mapping and recoding 2014-08-14 11:22:45 +02:00
Clifford Wolf 996c06f64d Added "abc -D" for setting delay target 2014-08-14 11:05:25 +02:00
Clifford Wolf a878095b46 Updated ABC to 4935c2b946de 2014-08-14 10:19:12 +02:00
Clifford Wolf 7e758d5fbb Added techmap support for actual lookahead carry unit 2014-08-13 18:40:57 +02:00
Clifford Wolf 9a065509ac Preparations for lookahead ALU support in techmap.v 2014-08-13 16:36:30 +02:00
Clifford Wolf 28bc7aeb93 Filter ANSI escape sequences from ABC output 2014-08-13 13:40:29 +02:00
Clifford Wolf c27120fcbc New interface for $__alu in techmap.v 2014-08-13 13:04:28 +02:00
Clifford Wolf f53984795d Added support for non-standard """ macro bodies 2014-08-13 13:03:38 +02:00
Clifford Wolf 9d353fc543 Fixed handling of constant-true branches in proc_clean 2014-08-12 17:35:22 +02:00
Clifford Wolf 1dd8252169 Added test_verific mode to tests/fsm/generate.py 2014-08-12 15:43:30 +02:00
Clifford Wolf e5ac8fdf2b Fixed SigBit(RTLIL::Wire *wire) constructor 2014-08-12 15:39:48 +02:00
Clifford Wolf 593264e9ed Fixed building verific bindings 2014-08-12 15:21:06 +02:00
Clifford Wolf cad98bcd89 Added multi-dim memory test (requires iverilog git head) 2014-08-12 10:37:47 +02:00
Clifford Wolf 5215723c64 Another build fix by americanrouter (via reddit) 2014-08-11 15:55:41 +02:00
Clifford Wolf 788bd02f97 Fixed FSM mapping for multiple reset-like signals 2014-08-10 12:04:02 +02:00
Clifford Wolf 9d4362990f Fixed "share" for complex scenarios with never-active cells 2014-08-09 17:07:20 +02:00
Clifford Wolf b9811d5aff Do not share any $reduce_* cells (its complicated and not worth it anyways) 2014-08-09 15:40:25 +02:00
Clifford Wolf 2faef89738 Some improvements in fsm_opt and fsm_map for FSM with unreachable states 2014-08-09 14:49:51 +02:00
Clifford Wolf 51aa5544fb Improved FSM tests 2014-08-08 15:08:11 +02:00
Clifford Wolf 58ac605470 Another fsm_extract bugfix 2014-08-08 14:56:04 +02:00
Clifford Wolf 7067c43ec0 Fixed "fsm -export" 2014-08-08 14:56:03 +02:00