eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
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frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
d1c8837572
Merge pull request #2000 from whitequark/log_error-trap
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kernel: Trap in `log_error()` when a debugger is attached
2020-05-03 16:19:42 +00:00
e9f2d3f009
kernel: Trap in `log_error()` when a debugger is attached.
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The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
1. Running Yosys under a debugger is sufficient for the debugger
to catch some fatal errors (segfaults, aborts, STL exceptions)
but not others (`log_error()`, `log_cmd_error()`). This is
neither obvious nor easy to remember.
2. To catch Yosys-specific fatal errors, it is necessary to set
a breakpoint at `logv_error_with_prefix()`, or at least,
`logv_error()`. This is neither obvious nor easy to remember,
and GDB's autocomplete takes many seconds to suggest function
names due to the large amount of symbols in Yosys.
3. If a breakpoint is not set and Yosys encounters with such
a fatal error, the process terminates. When debugging a crash
that takes a long time to reproduce (or a nondeterministic crash)
this can waste a significant amount of time.
To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.
Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.
Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
2020-05-03 12:02:34 +00:00
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
7360155459
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes
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aiger: fixes for ports that have start_offset != 0
2020-05-02 14:16:10 -07:00
2285cf1219
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:50:43 +02:00
885deb4e88
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:34:24 +02:00
da7da44919
abc9_ops: -reintegrate to be sensitive to start_offset too
2020-05-02 11:19:04 -07:00
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
c3e5a070ea
Add plusargs for output files in test_autotb output
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt
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Fix "opt_expr -fine" bug introduced in 213a89558
2020-05-02 11:20:02 +02:00
ff7a8d0e1e
Update ABC to include WASI support fixes.
2020-05-02 00:18:33 +00:00
b36060cc20
Fix WASI builds with abc enabled.
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This PR works around #2011 .
2020-05-01 23:57:35 +00:00
bbde241942
Merge pull request #2001 from whitequark/wasi
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Add WASI platform support
2020-05-01 21:28:20 +00:00
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
8ee32adac3
Fix "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-01 20:12:16 +02:00
667f38fe53
Merge pull request #1997 from whitequark/document-ootb
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Explain how to do out-of-tree builds in README
2020-05-01 15:35:33 +02:00
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
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Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
bc380b0b56
Merge pull request #1999 from YosysHQ/eddie/verific_enum_again
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verific: recover wiretype/enum attr as part of import_attributes()
2020-04-30 09:07:02 -07:00
33c9c04561
Merge pull request #2008 from whitequark/editorconfig-abc
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Fix .editorconfig to not break abc
2020-04-30 15:53:27 +00:00
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
adeed6f730
Fix .editorconfig to not break abc.
2020-04-30 02:22:37 +00:00
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
a66200ed1d
Merge pull request #1946 from YosysHQ/eddie/yosyshq_abc
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abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
2020-04-27 13:48:50 -07:00
c34d57de2e
Update CHANGELOG and manual for departure from upstream
2020-04-27 12:08:45 -07:00
a3fa9fd6e9
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
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Enabling modifications
2020-04-27 12:03:40 -07:00
eabc00de8b
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help
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bugpoint: improve help text
2020-04-27 11:12:17 -07:00
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
868b6b1b0d
Merge pull request #2002 from YosysHQ/dave/cxxrtl-width
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cxxrtl: Round up constant width
2020-04-25 18:30:53 +00:00
1b93dda037
cxxrtl: Round up constant width
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-25 10:42:21 +01:00
9b26a1fa89
README: explain how to do out-of-tree builds.
2020-04-24 23:27:43 +00:00
f1087b2552
Fix out-of-tree builds configured as `SMALL := 1`.
2020-04-24 23:27:43 +00:00
26cda3c247
gowin,ecp5: remove generated files in `make clean`.
2020-04-24 23:26:39 +00:00
bbf343589b
Merge pull request #1998 from whitequark/cxxrtl-fixes
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cxxrtl: fix attribute syntax, minor fixes
2020-04-24 22:44:35 +00:00
56dd036b97
bugpoint: improve messaging
2020-04-24 13:41:19 -07:00
e602184856
bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells
2020-04-24 13:26:04 -07:00
b52eccef3a
Revert "verific: import enum attributes from verific"
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This reverts commit 5028e17f7d
2020-04-24 11:57:55 -07:00
a0e658d412
cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.`
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The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
2020-04-24 18:35:53 +00:00
4bfe6ebea9
bugpoint: skip ports with (* keep *) on; add header
2020-04-24 11:17:09 -07:00
Eddie Hung
whitequark
Claire Wolf
Claire Wolf
Alberto Gonzalez
David Shah