This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.
This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.
The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
The return value of the min(...) call is never used.
Looks like some leftover from some previous implementation.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
Primitives are added to convert parallel signals to serial and vice versa.
IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If two methods have the same signature but for qualifiers the Python
binding doesn't care about ('const'), do not generate a mangled name for
the method.
Fixes
.def<Wire (Module::*)(const IdString* )>("wire__YOSYS_NAMESPACE_RTLIL_IdString", &Module::wire__YOSYS_NAMESPACE_RTLIL_IdString)
.def<Cell (Module::*)(const IdString* )>("cell__YOSYS_NAMESPACE_RTLIL_IdString", &Module::cell__YOSYS_NAMESPACE_RTLIL_IdString)
in the output after the previous change.
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
Aki Van Ness
Ralf Fuest
YRabbit
Jannis Harder
github-actions[bot]
Benjamin Barzen
AdamHillier
Henner Zeller
Miodrag Milanovic
gatecat
Martin Povišer
Stefan Riesenberger
Dag Lem