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12756 Commits

Author SHA1 Message Date
github-actions[bot] 8bd681acfc Bump version 2023-12-04 00:16:38 +00:00
gatecat bf955cc2b0 nexus: Fix format strings to remove space padding 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-03 10:36:34 +01:00
github-actions[bot] 8614d9b32f Bump version 2023-11-29 00:16:09 +00:00
Catherine 62bbd086b1 cxxrtl: reorganize runtime component files. 
In preparation for substantial expansion of CXXRTL's runtime, this commit
reorganizes the files used by the implementation. Only minimal changes are
required in a consumer.

First, change:
  -I$(yosys-config --datdir)/include
to:
  -I$(yosys-config --datdir)/include/backends/cxxrtl/runtime

Second, change:
  #include <backends/cxxrtl/cxxrtl.h>
to:
  #include <cxxrtl/cxxrtl.h>
(and do the same for cxxrtl_vcd.h, etc.)
 2023-11-28 15:32:36 +00:00
Catherine 3dd5262355 Add *.dwo files to .gitignore 
These files are generated in `-gsplit-dwarf` builds, which provide faster linking.
 2023-11-28 12:12:03 +00:00
N. Engelhardt beaae79e73
Merge pull request #4021 from povik/booth-wallace 
Change `booth` architecture for improved delay, similar signed/unsigned results
 2023-11-27 16:26:03 +01:00
github-actions[bot] 031ad38b5c Bump version 2023-11-24 00:15:38 +00:00
Miodrag Milanović 5e603c2241
Merge pull request #4042 from YosysHQ/verific_cell 
Verific: Add attributes to module instantiation
 2023-11-23 11:38:01 +01:00
Miodrag Milanovic 8f207eed1b Add attributes to module instantiation 2023-11-23 11:01:49 +01:00
Martin Povišer de16cd253d synth_lattice: Enable `booth` by default on XO3 2023-11-22 15:47:11 +01:00
Martin Povišer d6566eb344 booth: Redo baseline architecture summation 
Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
 2023-11-22 15:47:11 +01:00
Martin Povišer beb5cb55a5 booth: Expose `-lowpower` option 2023-11-22 15:29:59 +01:00
Martin Povišer 7005ea9411 booth: Revisit help 2023-11-22 15:29:59 +01:00
Martin Povišer 48b73be8c6 booth: Replace the default signed architecture 
Generalize what was formerly the unsigned-only architecture to support
both signed and unsigned multiplication, use that as default, and set
aside the special low-power architecture that was formerly used for
signed multipliers.
 2023-11-22 15:29:59 +01:00
Martin Povišer f50894d8bf booth: Drop extra decoder arguments 2023-11-22 15:29:54 +01:00
Martin Povišer 579f6bdc17 booth: Do not special-case bottom rows 
Later on all the rows are cropped to the target size anyway, so there's
no harm in transitionally including extra top bits.
 2023-11-22 15:12:15 +01:00
Martin Povišer da207cdce0 booth: Make less assumptions when aligning partial products 2023-11-22 15:12:15 +01:00
Martin Povišer 69e994ff75 booth: Clean unused FA index variable 2023-11-22 12:47:09 +01:00
Martin Povišer d8408b2350 booth: Move up signed quadrant 1 logic 2023-11-22 12:46:15 +01:00
Martin Povišer 8d33cc2fb6 booth: Refactor signed CPA 2023-11-22 12:46:15 +01:00
Martin Povišer 00e899f98d booth: Refactor signed multiplier full adders emission 2023-11-22 12:46:15 +01:00
Martin Povišer 84568453f8 rtlil: Add `lsb()` `msb()` SigSpec helpers 2023-11-22 12:46:15 +01:00
github-actions[bot] c95298225d Bump version 2023-11-21 00:16:08 +00:00
Martin Povišer 34f851f132
Merge pull request #4040 from povik/fmt-time 
fmt: Handle free-standing time arguments
 2023-11-20 18:11:24 +01:00
Martin Povišer 282ce24eec fmt: Handle free-standing time arguments 2023-11-20 17:25:42 +01:00
Jannis Harder b23a607421
Merge pull request #4035 from jix/smtbmc-incremental 
smtbmc: Add --incremental mode
 2023-11-20 17:00:29 +01:00
Miodrag Milanović 191ac91951
Merge pull request #4031 from nakengelhardt/nak/fix_vhdl_blackbox_nullptr 
verific: don't try to import attributes from nullptr
 2023-11-20 15:37:01 +01:00
github-actions[bot] ab6c1d368b Bump version 2023-11-18 00:15:31 +00:00
N. Engelhardt fa5fb811df
Merge pull request #4037 from YosysHQ/lofty/ice40-abc9-oopsie 
ice40: fix -noabc9
 2023-11-17 14:36:16 +01:00
Lofty 5c96746309 ice40: fix -noabc9 2023-11-17 12:49:17 +00:00
Jannis Harder e319606ec9 smtbmc: Add --incremental mode 2023-11-16 13:22:17 +01:00
N. Engelhardt 032fab1f54
Merge pull request #4032 from YosysHQ/lofty/gowin-abc9-oopsie 
gowin: fix typo
 2023-11-15 11:07:49 +01:00
github-actions[bot] 7eea047793 Bump version 2023-11-15 00:15:49 +00:00
Lofty 309558767d gowin: fix typo 2023-11-14 22:37:29 +00:00
N. Engelhardt 5fb1264db5 verific: don't try to import attributes from nullptr 2023-11-14 15:05:24 +01:00
Catherine c11744b4ef
Fix WASI compilation flags for abc. 2023-11-14 03:33:35 +00:00
Catherine 726c501e7e Update WASI compilation flags to include required libraries 2023-11-14 02:05:39 +00:00
github-actions[bot] 46408b5da3 Bump version 2023-11-14 00:15:32 +00:00
N. Engelhardt 8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again 
ice40, ecp5, gowin: enable ABC9 by default
 2023-11-13 17:29:57 +01:00
N. Engelhardt 52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work 
MachXO3 QoR improvements
 2023-11-13 16:56:06 +01:00
N. Engelhardt 3fef81b537
Merge pull request #4028 from povik/cmp2softlogic 
synth_lattice: Optionally do constant comparisons in soft logic
 2023-11-13 16:53:04 +01:00
Jannis Harder 6cf50d16a8
Merge pull request #3973 from anonkey/master 
cli(tcl): add ability to pass argument to tcl script from cli
 2023-11-13 16:29:05 +01:00
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
N. Engelhardt 04083b4f15
Merge pull request #4027 from YosysHQ/achronix_typo 
Fix typo in help message (Acrhonix -> Achronix)
 2023-11-13 16:04:24 +01:00
Martin Povišer 3ffa4b5e5d synth_lattice: Wire up `cmp2softlogic` as an option 2023-11-13 10:42:12 +01:00
Martin Povišer f7d4a855c6 techlibs: Add `cmp2softlogic.v` to common 2023-11-13 10:42:12 +01:00
Krystine Sherwin 83d2f4f334
techlibs: fix typo in help message 2023-11-13 16:29:52 +13:00
github-actions[bot] 5691cd0958 Bump version 2023-11-08 00:15:30 +00:00
Martin Povišer fed2720999 synth_lattice: Optimize flip-flop memories better 
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
 2023-11-07 16:29:56 +01:00
Martin Povišer ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals 
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
 2023-11-07 16:21:39 +01:00