mirror of https://github.com/YosysHQ/yosys.git
synth_lattice: Merge NOT gates on DFF control signals
`dfflegalize` will emit NOT gates to drive control signals on flip-flops when mapping to supported flip-flop polarities. Typically in a design this will produce a number of NOT gates driven by the same signal. For one reason or another ABC doesn't fully cancel this redundancy during LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis QoR.
This commit is contained in:
parent
63cec22a0c
commit
ee3a4ce14d
|
@ -409,6 +409,7 @@ struct SynthLatticePass : public ScriptPass
|
|||
dfflegalize_args += " -cell $_DLATCH_?_ x";
|
||||
}
|
||||
run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
|
||||
run("opt_merge");
|
||||
if ((abc9 && dff) || help_mode)
|
||||
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
|
||||
run("techmap -D NO_LUT -map +/lattice/cells_map.v");
|
||||
|
|
Loading…
Reference in New Issue