mirror of https://github.com/YosysHQ/yosys.git
Added test for dynamic indexing within struct members
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module range_shift_mask(
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input logic [2:0] addr_i,
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input logic [7:0] data_i,
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input logic [2:0] addr_o,
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output logic [7:0] data_o
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);
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// (* nowrshmsk = 0 *)
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struct packed {
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logic [7:0] msb;
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logic [0:3][7:0] data;
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logic [7:0] lsb;
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} s;
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always_comb begin
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s = '1;
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s.data[addr_i] = data_i;
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data_o = s.data[addr_o];
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end
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endmodule
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module range_case(
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input logic [2:0] addr_i,
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input logic [7:0] data_i,
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input logic [2:0] addr_o,
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output logic [7:0] data_o
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);
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// (* nowrshmsk = 1 *)
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struct packed {
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logic [7:0] msb;
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logic [0:3][7:0] data;
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logic [7:0] lsb;
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} s;
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always_comb begin
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s = '1;
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s.data[addr_i] = data_i;
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data_o = s.data[addr_o];
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end
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endmodule
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module top;
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logic [7:0] data_shift_mask1;
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range_shift_mask range_shift_mask1(3'd1, 8'h7e, 3'd1, data_shift_mask1);
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logic [7:0] data_shift_mask2;
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range_shift_mask range_shift_mask2(3'd1, 8'h7e, 3'd2, data_shift_mask2);
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logic [7:0] data_shift_mask3;
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range_shift_mask range_shift_mask3(3'd1, 8'h7e, 3'd4, data_shift_mask3);
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always_comb begin
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assert(data_shift_mask1 === 8'h7e);
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assert(data_shift_mask2 === 8'hff);
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assert(data_shift_mask3 === 8'hxx);
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end
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logic [7:0] data_case1;
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range_case range_case1(3'd1, 8'h7e, 3'd1, data_case1);
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logic [7:0] data_case2;
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range_case range_case2(3'd1, 8'h7e, 3'd2, data_case2);
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logic [7:0] data_case3;
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range_case range_case3(3'd1, 8'h7e, 3'd4, data_case3);
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always_comb begin
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assert(data_case1 === 8'h7e);
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assert(data_case2 === 8'hff);
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assert(data_case3 === 8'hxx);
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end
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endmodule
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@ -0,0 +1,4 @@
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read_verilog -sv struct_dynamic_range.sv
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prep -top top
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flatten
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sat -enable_undef -verify -prove-asserts
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