riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,064 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

7064 Commits

Author SHA1 Message Date
Eddie Hung 36cf0a3dd5 Remove adffs_tb.v 2019-08-22 16:50:14 -07:00
Eddie Hung 51ffb093b5 In sat: 'x' in init attr should not override constant 2019-08-22 16:43:08 -07:00
Eddie Hung 2b37a093e9 In sat: 'x' in init attr should not override constant 2019-08-22 16:42:19 -07:00
Eddie Hung 66607845ec Remove Xilinx test 2019-08-22 16:18:07 -07:00
Eddie Hung 53fed4f7e9 Actually, there might not be any harm in updating sigmap... 2019-08-22 16:16:56 -07:00
Eddie Hung cfafd360d5 Add comment as per @cliffordwolf 2019-08-22 16:16:56 -07:00
Eddie Hung e7a8cdbccf Add shregmap -tech xilinx test 2019-08-22 16:16:54 -07:00
Eddie Hung 8691596d19 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-08-22 16:16:34 -07:00
Eddie Hung 5ff75b1cdc Try way that doesn't involve creating a new wire 2019-08-22 16:16:34 -07:00
Eddie Hung e1fff34dde If d_bit already in sigbit_chain_next, create extra wire 2019-08-22 16:16:34 -07:00
Eddie Hung c50d68653d Spelling 2019-08-22 16:06:36 -07:00
Eddie Hung 698a0e3aaf WIP for equivalency checking memories 2019-08-22 16:05:12 -07:00
Eddie Hung 43e7c4917a Do not print OKAY 2019-08-22 16:05:12 -07:00
Eddie Hung 65e6c23abd Spelling 2019-08-22 16:05:12 -07:00
Eddie Hung 5061d239ae Fail if iverilog fails 2019-08-22 16:05:12 -07:00
Eddie Hung 8e3754bdb4 Hide tri-state warning message for now 2019-08-22 16:05:12 -07:00
Eddie Hung 659a481482 Remove unused output 2019-08-22 16:05:12 -07:00
Eddie Hung 61087329ef Fix tribuf test 2019-08-22 16:05:12 -07:00
Eddie Hung f9906eed68 Fix comments 2019-08-22 16:05:12 -07:00
Eddie Hung 9224b3bc17 Remove tech independent synthesis 2019-08-22 16:05:12 -07:00
Eddie Hung 388eb3288c Remove dffe instantation 2019-08-22 16:04:50 -07:00
Eddie Hung 9e537a76b5 Move $dffe to dffs.{v,ys} 2019-08-22 16:04:48 -07:00
Eddie Hung c5754d9e8b Make multiplier wider, do not do tech independent synth 2019-08-22 16:04:07 -07:00
Miodrag Milanovic 7fafaa896d do not require boost if pyosys is not used 2019-08-22 11:57:46 -07:00
Chris Shucksmith 68e673d687 require tcl-tk in Brewfile 2019-08-22 11:57:25 -07:00
Eddie Hung 2fe35f902b
Merge pull request #1322 from mmicko/pyosys_osx 
do not require boost if pyosys is not used
 2019-08-22 11:53:27 -07:00
Eddie Hung 6e8fda8bf0 Add doc 2019-08-22 11:52:24 -07:00
Miodrag Milanovic e5dac8096d do not require boost if pyosys is not used 2019-08-22 20:43:52 +02:00
Eddie Hung 926cd10350
Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk 
require tcl-tk in Brewfile
 2019-08-22 11:32:44 -07:00
Eddie Hung cabadb85e2 Add copyright 2019-08-22 11:25:19 -07:00
Eddie Hung 7a9031c48e Add CHANGELOG entry 2019-08-22 11:22:53 -07:00
Eddie Hung 36d94caec1 Remove `shregmap -tech xilinx` additions 2019-08-22 11:22:09 -07:00
Eddie Hung 9f3ed1726e pmgen to also iterate over all module ports 2019-08-22 11:15:16 -07:00
Eddie Hung 74bd190d3b Remove output_bits 2019-08-22 11:14:59 -07:00
Eddie Hung 231ddbf95c Forgot to set ud_variable.minlen 2019-08-22 11:02:17 -07:00
Eddie Hung 61639d5387 Do not run xilinx_srl_pm in fixed loop 2019-08-22 10:51:04 -07:00
Eddie Hung 7188972645 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:54 -07:00
Eddie Hung d0b2973413 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:06 -07:00
Eddie Hung b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Clifford Wolf 5e0f6c9ae5 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:54 +02:00
Clifford Wolf e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Clifford Wolf 2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes 
Anlogic fixes and optimization
 2019-08-22 18:09:10 +02:00
Clifford Wolf 4c449caf9b Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:06:36 +02:00
Clifford Wolf 4d37710e82
Merge pull request #1281 from mmicko/efinix 
Initial support for Efinix Trion series FPGAs
 2019-08-22 18:06:02 +02:00
Eddie Hung 9245f0d3f5 Copy-paste typo 2019-08-22 08:43:44 -07:00
Chris Shucksmith d0322e9584 require tcl-tk in Brewfile 2019-08-22 16:37:40 +01:00
Eddie Hung 6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung 379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung 9e31f01b34 Add cover() 2019-08-22 08:06:24 -07:00