riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,866 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

4866 Commits

Author SHA1 Message Date
Clifford Wolf 84f3a796e1 Include filename in "Executing Verilog-2005 frontend" message, fixes #959 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:37:46 +02:00
Clifford Wolf 9268cd1613 Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:19:10 +02:00
Clifford Wolf 314ff1e4ca
Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef 
Add -undef option to equiv_opt, passed to equiv_induct
 2019-04-29 13:54:26 +02:00
Clifford Wolf 8fde245ea2
Merge pull request #967 from olegendo/depfile_esc_spaces 
escape spaces with backslash when writing dep file
 2019-04-29 13:48:52 +02:00
Oleg Endo 4f15e7f00f fix codestyle formatting 2019-04-29 19:20:33 +09:00
Oleg Endo e531fb203a escape spaces with backslash when writing dep file 
filenames are sparated by spaces in the dep file.  if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
 2019-04-29 16:13:34 +09:00
Eddie Hung ea0e0722bb Where did this check come from!?! 2019-04-26 15:35:34 -07:00
Eddie Hung 159e7cc298 Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
Eddie Hung 408161ea3a
Misspelling 2019-04-25 16:46:13 -07:00
Clifford Wolf b2020ab44f
Merge pull request #957 from YosysHQ/oai4fix 
Fixes for OAI4 cell implementation
 2019-04-23 19:59:39 +02:00
David Shah 742c2f245d Fixes for OAI4 cell implementation 
Fixes #955 and the underlying issue in #954

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-23 17:54:00 +01:00
Eddie Hung c6156f3118
Format some names using inline code 2019-04-23 09:01:10 -07:00
Eddie Hung f66792c43a
Fix spelling 2019-04-23 08:58:34 -07:00
Clifford Wolf c84cdc711c Remove some left-over log_dump() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 17:55:41 +02:00
Eddie Hung d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl 
synth_xilinx to now infer SRL16E/SRLC32E
 2019-04-22 13:31:30 -07:00
Eddie Hung ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Clifford Wolf bc98a463a4
Merge pull request #952 from YosysHQ/clifford/fix370 
Determine correct signedness and expression width in for-loop unrolling
 2019-04-22 20:10:46 +02:00
Clifford Wolf 8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug 
Add log_debug() framework
 2019-04-22 20:09:51 +02:00
Clifford Wolf 1d538ff1ec
Merge pull request #949 from YosysHQ/clifford/pmux2shimprove 
Add full_pmux feature to pmux2shiftx
 2019-04-22 20:01:43 +02:00
Clifford Wolf 3be5aac52c
Merge pull request #953 from YosysHQ/clifford/fix948 
Add support for zero-width signals to Verilog back-end
 2019-04-22 20:01:09 +02:00
Eddie Hung 0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00
Clifford Wolf 0e0c80fac8 Add support for zero-width signals to Verilog back-end, fixes #948 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 19:44:42 +02:00
Eddie Hung e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf 4ad0ea5c3c Determine correct signedness and expression width in for loop unrolling, fixes #370 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 18:19:02 +02:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
Clifford Wolf 9050b5e191
Merge pull request #950 from whitequark/attrmap_remove_wildcard 
attrmap: extend -remove to allow removing attributes with any value
 2019-04-22 16:54:38 +02:00
whitequark aeeefc32d8 attrmap: extend -remove to allow removing attributes with any value. 
Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.
 2019-04-22 14:18:15 +00:00
Clifford Wolf a80e74dc20 Updaye pmux2shiftx test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 16:17:43 +02:00
Clifford Wolf 0f0ada13f4 Add full_pmux feature to pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 15:26:20 +02:00
Clifford Wolf c0f9a74b12 Set ENABLE_LIBYOSYS=0 by default 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 14:59:30 +02:00
Clifford Wolf 93f32b5dec Set ENABLE_PYOSYS=0 by default 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 14:49:17 +02:00
Clifford Wolf 99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings 
Feature/python bindings
 2019-04-22 14:47:52 +02:00
Clifford Wolf 0e7901e45c
Merge pull request #941 from Wren6991/sim_lib_io_clke 
ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
 2019-04-22 09:11:13 +02:00
Clifford Wolf c1dfc7ca96 Merge branch 'dh73-master' 2019-04-22 09:10:07 +02:00
Clifford Wolf 913659d644 Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
Clifford Wolf cf1ba46fa0 Re-added clean after techmap in synth_xilinx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 09:03:11 +02:00
Clifford Wolf cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts 
synth_xilinx to map_cells before map_luts
 2019-04-22 09:01:00 +02:00
Clifford Wolf 19fd411e77
Merge pull request #911 from mmicko/gowin-nobram 
Make nobram false by default for gowin
 2019-04-22 08:58:09 +02:00
Clifford Wolf b40af877f3
Merge pull request #909 from zachjs/master 
support repeat loops with constant repeat counts outside of constant functions
 2019-04-22 08:51:34 +02:00
Clifford Wolf a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx 
Add pmux2shiftx command
 2019-04-22 08:39:37 +02:00
Clifford Wolf 632a666448
Merge pull request #945 from YosysHQ/clifford/libwb 
New behavior for read_verilog handling of whiteboxes
 2019-04-22 08:38:52 +02:00
Clifford Wolf 7b35d57592 Disable blackbox detection in techmap files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 02:07:36 +02:00
Eddie Hung d342b5b135 Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
Eddie Hung 726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
Eddie Hung a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Eddie Hung ae95aba60a Add comments 2019-04-21 14:16:59 -07:00
Eddie Hung d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Luke Wren 71da836300 ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments 2019-04-21 21:40:11 +01:00
Clifford Wolf d38f0c1a96 Fix tests 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:20 +02:00
Clifford Wolf 5b7fea5245 Add "noblackbox" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:09 +02:00