riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,069 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

5069 Commits

Author SHA1 Message Date
Eddie Hung 070a2d2fd6 Fix abc's remap_name to not ignore [^0-9] when extracting sid 2019-04-18 09:55:03 -07:00
Eddie Hung 9aa94370a5 ABC to call retime all the time 2019-04-18 08:46:41 -07:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Eddie Hung 6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well" 
This reverts commit 9a6da9a79a.
 2019-04-18 07:59:16 -07:00
Eddie Hung 0642baabbc Merge branch 'master' into eddie/fix_retime 2019-04-18 07:57:17 -07:00
Clifford Wolf 88be1cbfa5 Improve proc full_case detection and handling, fixes #931 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 15:13:47 +02:00
Clifford Wolf ea8ac0aaad Update to ABC d1b6413 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-17 13:51:34 +02:00
Eddie Hung 2df7d97b72
Merge pull request #939 from YosysHQ/revert895 
Revert #895 (mux-to-shiftx optimisation)
 2019-04-16 11:59:21 -07:00
Eddie Hung 4da4a6da2f Revert #895 2019-04-16 11:07:51 -07:00
Eddie Hung dca45c0888
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch 
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
 2019-04-15 18:39:20 -07:00
Eddie Hung b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
Eddie Hung 18a4045858
Merge pull request #936 from YosysHQ/README-fix-quotes 
README: fix some incorrect quoting
 2019-04-15 12:22:05 -07:00
whitequark 6323e73cc9
README: fix some incorrect quoting. 2019-04-15 14:29:46 +00:00
Diego f9272fc56d GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
Eddie Hung db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models 
Add additional cells sim models for core 7-series primitives.
 2019-04-12 11:52:45 -07:00
Keith Rothman 1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Clifford Wolf 9d6586b4e1
Merge pull request #933 from dh73/master 
Fixing issues in CycloneV cell sim
 2019-04-12 14:57:36 +02:00
Clifford Wolf 48bc203653
Merge pull request #932 from YosysHQ/eddie/fixdlatch 
Recognise default entry in case even if all cases covered (fix for #931)
 2019-04-12 14:57:01 +02:00
Diego 643ae9bfc5 Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
Eddie Hung 3c1f1a6605 Fix ordering of when to insert zero index 2019-04-11 16:25:59 -07:00
Eddie Hung f587950bde More unused 2019-04-11 16:20:43 -07:00
Eddie Hung b15b410b41 Remove unused 2019-04-11 16:18:01 -07:00
Eddie Hung b1f1db2fcf Fixes 2019-04-11 16:17:09 -07:00
Eddie Hung e8c26f2839 WIP 2019-04-11 15:52:04 -07:00
Eddie Hung 09e7eb7aed Spelling fixes 2019-04-11 15:09:13 -07:00
Eddie Hung 7685469ee2 Add default entry to testcase 2019-04-11 15:03:40 -07:00
Eddie Hung adc6efb584 Recognise default entry in case even if all cases covered (#931) 2019-04-11 12:34:51 -07:00
Eddie Hung 9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Eddie Hung 5f4024ffd2 Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen" 
This reverts commit 19271bd996.
 2019-04-10 08:31:40 -07:00
Eddie Hung 78d35a86c0 Revert ""&nf -D 0" fails => use "-D 1" instead" 
This reverts commit 3c253818ca.
 2019-04-10 08:31:35 -07:00
Eddie Hung c89cd48f58 Merge remote-tracking branch 'origin/master' into eddie/fix_retime 2019-04-10 08:23:00 -07:00
Jim Lawson 354ba5ba83 Merge remote-tracking branch 'upstream/master' 2019-04-09 13:41:58 -07:00
Keith Rothman e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Zachary Snow 5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Keith Rothman 5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
Eddie Hung 0deaccbaae
Fix a few typos 2019-04-08 16:46:33 -07:00
Eddie Hung 6797f6b6c4 $_XILINX_SHREG_ to preserve src attribute 2019-04-08 16:24:20 -07:00
Eddie Hung f6c354c55b Update CHANGELOG 2019-04-08 16:22:07 -07:00
Eddie Hung 7e773741ab Merge branch 'undo_pr895' into xc7srl 2019-04-08 16:07:52 -07:00
Eddie Hung 13fc70d7a4 Undo #895 by instead setting an attribute 2019-04-08 16:05:24 -07:00
Eddie Hung 93b1621911 Cope with undoing #895 2019-04-08 15:57:07 -07:00
Clifford Wolf e194e65358
Merge pull request #919 from YosysHQ/multiport_transp 
memory_bram: Fix multiport make_transp
 2019-04-08 21:14:05 +02:00
Eddie Hung d3930ca79e Revert "Remove handling for $pmux, since #895" 
This reverts commit aa693d5723.
 2019-04-08 12:01:06 -07:00
David Shah 2bf3ca6443 memory_bram: Fix multiport make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-07 16:56:31 +01:00
Benedikt Tutzer e19981ab61 Suppress error from the compiler run during libboost-python* detection 2019-04-07 10:11:35 +02:00
Eddie Hung 1d526b7f06 Call shregmap twice -- once for variable, another for fixed 2019-04-05 17:35:49 -07:00
Eddie Hung 4afcad70e2 Merge branch 'eddie/fix_retime' into xc7srl 2019-04-05 16:30:17 -07:00
Eddie Hung ad602438b8 Add retime test 2019-04-05 16:28:46 -07:00
Eddie Hung d559023007 Fix S0 -> S1 2019-04-05 16:28:14 -07:00
Eddie Hung a5f33b5409 Move dffinit til after abc 2019-04-05 16:20:43 -07:00