Merge pull request #932 from YosysHQ/eddie/fixdlatch

Recognise default entry in case even if all cases covered (fix for #931)
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Clifford Wolf 2019-04-12 14:57:01 +02:00 committed by GitHub
commit 48bc203653
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2 changed files with 4 additions and 3 deletions

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@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
for (size_t i = 0; i < sw->cases.size(); i++)
{
bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0);
bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0;
for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
RTLIL::SigSpec sig = sw->cases[i]->compare[j];

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@ -8,12 +8,13 @@ read_verilog -formal <<EOT
3'b?1?: Y = B;
3'b1??: Y = C;
3'b000: Y = D;
default: Y = 'bx;
endcase
endmodule
EOT
## Examle usage for "pmuxtree" and "muxcover"
## Example usage for "pmuxtree" and "muxcover"
proc
pmuxtree
@ -35,7 +36,7 @@ read_verilog -formal <<EOT
3'b010: Y = B;
3'b100: Y = C;
3'b000: Y = D;
default: Y = 'bx;
default: Y = 'bx;
endcase
endmodule
EOT