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5328 Commits

Author SHA1 Message Date
Clifford Wolf 76f20492a4 Merge pull request #1162 from whitequark/rtlil-case-attrs 
Allow attributes on individual switch cases in RTLIL
 2019-07-09 18:48:38 +01:00
Clifford Wolf 17e0cc010c Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire 
Throw runtime exception when trying to convert inexistend C++ object to Python
 2019-07-09 18:48:23 +01:00
Clifford Wolf fecd3aa2b1 Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-09 18:47:08 +01:00
Clifford Wolf d105e2f03f Merge pull request #1154 from whitequark/manual-sync-always 
manual: explain the purpose of `sync always`
 2019-07-09 18:46:58 +01:00
David Shah 4b49c0201e Merge pull request #1153 from YosysHQ/dave/fix_multi_mux 
memory_dff: Fix checking of feedback mux input when more than one mux
 2019-07-09 18:46:39 +01:00
Clifford Wolf 7b298479d4 Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 18:46:28 +01:00
Eddie Hung fc87c010c5 autotest.sh to define _AUTOTB when test_autotb 2019-07-09 18:46:18 +01:00
Clifford Wolf ef0823690c Merge pull request #1146 from gsomlo/gls-test-abc-ext 
tests: use optional ABCEXTERNAL when specified
 2019-07-09 18:44:57 +01:00
Eddie Hung 43069e9eb9 Checkout yosys-0.9-rc branch of yosys-tests 2019-07-02 10:06:56 -07:00
Eddie Hung fdf0e82472 Add missing CHANGELOG entries 2019-06-28 11:16:53 -07:00
Eddie Hung c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog 
tests: Check that Icarus can parse arch sim models
 2019-06-27 12:31:15 -07:00
Eddie Hung eab8384ec7 Grr 2019-06-27 11:53:42 -07:00
Eddie Hung 36f3cc9dcc Capitalisation 2019-06-27 11:50:12 -07:00
Eddie Hung d5cfe341f9 Make CHANGELOG clearer 2019-06-27 11:50:12 -07:00
Eddie Hung 6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135 
Add "pmux2shiftx -norange"
 2019-06-27 11:48:48 -07:00
Eddie Hung ab7c431905 Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00
Eddie Hung 18acb72c05 Add #1135 testcase 2019-06-27 11:02:52 -07:00
Eddie Hung 760819e10d synth_xilinx -arch -> -family, consistent with older synth_intel 2019-06-27 07:24:47 -07:00
Eddie Hung ee77ee6973
Merge pull request #1142 from YosysHQ/clifford/fix1132 
Fix handling of partial covers in muxcover
 2019-06-27 07:21:31 -07:00
Eddie Hung bb4ae8bc66
Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux 
synth_xilinx: Add -nocarry and -nowidelut options
 2019-06-27 06:04:56 -07:00
Eddie Hung 3910bc2ea6 Copy tests from eddie/fix1132 2019-06-27 06:01:50 -07:00
Clifford Wolf 7c14678ec0 Add "pmux2shiftx -norange", fixes #1135 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-27 10:59:12 +02:00
Clifford Wolf 69d810e4a8 Fix handling of partial covers in muxcover, fixes #1132 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-27 09:42:58 +02:00
Eddie Hung 6db181471e Grrr 2019-06-26 10:47:03 -07:00
David Shah 71b046d639 tests: Check that Icarus can parse arch sim models 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 18:46:22 +01:00
Eddie Hung 138989e1a3 Fix spacing 2019-06-26 10:09:18 -07:00
Eddie Hung cb722e7b58 Oops. Actually use nocarry flag as spotted by @koriakin 2019-06-26 10:06:33 -07:00
Clifford Wolf 0d2b87e3ed
Merge pull request #1137 from mmicko/cell_sim_fix 
Simulation model verilog fix
 2019-06-26 19:06:10 +02:00
Miodrag Milanovic ea0b6258ab Simulation model verilog fix 2019-06-26 18:34:34 +02:00
Eddie Hung 4ce329aefd synth_ecp5 rename -nomux to -nowidelut, but preserve former 2019-06-26 09:33:48 -07:00
Eddie Hung 7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
Clifford Wolf 0b7d648c6a Improve opt_clean handling of unused public wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:54:17 +02:00
Clifford Wolf 1b49380f6b Improve BTOR2 handling of undriven wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:42:00 +02:00
Clifford Wolf f6053b8810 Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:09:43 +02:00
Clifford Wolf 8e9ef891fe Do not clean up buffer cells with "keep" attribute, closes #1128 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:01:03 +02:00
Clifford Wolf b3c36b4448 Escape scope names starting with dollar sign in smtio.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 10:58:39 +02:00
whitequark 3d4102cfa4 Add more ECP5 Diamond flip-flops. 
This includes all I/O registers, and a few more regular FFs where it
was convenient.
 2019-06-26 01:57:29 +00:00
Eddie Hung ab6e8ce0f0 Add testcase from #335, fixed by #1130 2019-06-25 08:43:58 -07:00
Clifford Wolf add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710 
memory_dff: walk through more than one mux for computing read enable
 2019-06-25 17:34:44 +02:00
Eddie Hung 42720ef6fe Fix spacing 2019-06-25 08:33:17 -07:00
Eddie Hung c4e4902098 Move only one consumer check outside of while loop 2019-06-25 08:29:55 -07:00
Eddie Hung 58629dc2ce
Merge pull request #1129 from YosysHQ/eddie/ram32x1d 
Add RAM32X1D support
 2019-06-25 08:22:57 -07:00
Clifford Wolf e754bce047
Merge pull request #1075 from YosysHQ/eddie/muxpack 
Add new "muxpack" command for packing chains of $mux cells
 2019-06-25 17:21:59 +02:00
Eddie Hung b7deaceadd Walk through as many muxes as exist for rd_en 2019-06-24 18:33:06 -07:00
Eddie Hung a701a2accf Add test 2019-06-24 18:32:58 -07:00
Eddie Hung efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Clifford Wolf e32cef4063
Merge pull request #1124 from mmicko/json_ports 
Add upto and offset to JSON ports
 2019-06-24 08:52:12 +02:00
Eddie Hung 4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung fb8fab4a29 Add 'muxcover -dmux=<cost>' and '-nopartial' to CHANGELOG 2019-06-21 20:30:24 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00