mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1147 from YosysHQ/clifford/fix1144
Improve specify dummy parser
This commit is contained in:
Clifford Wolf
David Shah
parent
d105e2f03f
commit
fecd3aa2b1
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@ -1021,13 +1021,8 @@ list_of_specparam_assignments:
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specparam_assignment:
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ignspec_id '=' constant_mintypmax_expression ;
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/*
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pulsestyle_declaration :
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;
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showcancelled_declaration :
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;
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*/
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ignspec_opt_cond:
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TOK_IF '(' ignspec_expr ')' | /* empty */;
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path_declaration :
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simple_path_declaration ';'
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@ -1036,8 +1031,8 @@ path_declaration :
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;
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simple_path_declaration :
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parallel_path_description '=' path_delay_value |
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full_path_description '=' path_delay_value
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ignspec_opt_cond parallel_path_description '=' path_delay_value |
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ignspec_opt_cond full_path_description '=' path_delay_value
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;
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path_delay_value :
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@ -1047,32 +1042,20 @@ path_delay_value :
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;
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list_of_path_delay_extra_expressions :
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/*
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t_path_delay_expression
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| trise_path_delay_expression ',' tfall_path_delay_expression
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| trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
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| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
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tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
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| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
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tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
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t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
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tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
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*/
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',' path_delay_expression
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| ',' path_delay_expression ',' path_delay_expression
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| ',' path_delay_expression ',' path_delay_expression ','
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path_delay_expression ',' path_delay_expression ',' path_delay_expression
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| ',' path_delay_expression ',' path_delay_expression ','
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path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
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path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
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path_delay_expression ',' path_delay_expression ',' path_delay_expression
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;
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',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
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specify_edge_identifier :
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TOK_POSEDGE | TOK_NEGEDGE ;
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parallel_path_description :
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'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
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'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
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'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
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'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
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full_path_description :
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'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
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'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
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'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
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'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
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// This was broken into 2 rules to solve shift/reduce conflicts
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list_of_path_inputs :
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@ -1112,56 +1095,6 @@ system_timing_args :
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system_timing_arg |
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system_timing_args ',' system_timing_arg ;
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/*
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t_path_delay_expression :
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path_delay_expression;
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trise_path_delay_expression :
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path_delay_expression;
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tfall_path_delay_expression :
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path_delay_expression;
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tz_path_delay_expression :
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path_delay_expression;
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t01_path_delay_expression :
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path_delay_expression;
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t10_path_delay_expression :
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path_delay_expression;
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t0z_path_delay_expression :
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path_delay_expression;
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tz1_path_delay_expression :
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path_delay_expression;
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t1z_path_delay_expression :
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path_delay_expression;
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tz0_path_delay_expression :
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path_delay_expression;
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t0x_path_delay_expression :
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path_delay_expression;
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tx1_path_delay_expression :
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path_delay_expression;
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t1x_path_delay_expression :
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path_delay_expression;
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tx0_path_delay_expression :
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path_delay_expression;
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txz_path_delay_expression :
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path_delay_expression;
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tzx_path_delay_expression :
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path_delay_expression;
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*/
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path_delay_expression :
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ignspec_constant_expression;
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@ -7,9 +7,11 @@ module test (
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if (EN) Q <= D;
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specify
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if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
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`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
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if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
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$setup(D, posedge CLK &&& EN, 5);
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$hold(posedge CLK, D &&& EN, 6);
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`endif
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endspecify
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endmodule
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@ -28,3 +30,10 @@ module test2 (
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(B => Q) = 1.5;
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endspecify
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endmodule
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module issue01144(input clk, d, output q);
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specify
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(posedge clk => (q +: d)) = (3,1);
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(posedge clk *> (q +: d)) = (3,1);
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endspecify
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endmodule
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@ -54,3 +54,5 @@ equiv_struct
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equiv_induct -seq 5
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equiv_status -assert
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design -reset
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read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
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