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This commit is contained in:
Eddie Hung 2019-06-27 11:26:44 -07:00
parent d5cfe341f9
commit 36f3cc9dcc
1 changed files with 1 additions and 1 deletions
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@ -47,7 +47,7 @@ Yosys 0.7 .. Yosys 0.8
- Added Verilog $rtoi and $itor support
- Added "check -initdrv"
- Added "read_blif -wideports"
- Added support for systemVerilog "++" and "--" operators
- Added support for SystemVerilog "++" and "--" operators
- Added support for SystemVerilog unique, unique0, and priority case
- Added "write_edif" options for edif "flavors"
- Added support for resetall compiler directive