riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,519 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

12519 Commits

Author SHA1 Message Date
andyfox-rushc 6d29dc659b renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script 2023-09-08 15:34:56 -07:00
andyfox-rushc 411acc4a0a Fixed edge size cases for signed/unsigned booth generator 2023-09-08 13:41:31 -07:00
Martin Povišer 25a33d4082 techmap: Make the Booth test deterministic 2023-09-07 14:56:56 +02:00
Martin Povišer 0c2a99ca47 techmap: Test the Booth multiplier 2023-09-07 14:46:59 +02:00
andyfox-rushc fedefa26bc multpass -- create Booth Encoded multipliers for 2023-09-06 16:35:17 -07:00
Jannis Harder 368f2dd618
Merge pull request #3922 from jix/xprop-fixes 2023-09-06 20:29:17 +02:00
Jannis Harder e187fc915e xprop: Fix polarity errors and generate hdlnames 
* Fixes a non-deterministic polarity error for $eqx/$nex cells
* Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells
* Generates hdlnames when xprop is run after flatten
 2023-09-06 19:25:47 +02:00
github-actions[bot] 83b1a57eed Bump version 2023-09-06 00:14:34 +00:00
Martin Povišer d4d951657f sim: Add `-assert` option to fail on failed assertions 2023-09-05 10:46:04 +02:00
Martin Povišer e995dddeaa abc: Warn about replacing undef bits 2023-09-05 10:45:30 +02:00
Miodrag Milanovic 11a2de815a Next dev cycle 2023-09-05 08:11:03 +02:00
Miodrag Milanovic 2584903a06 Release version 0.33 2023-09-05 08:08:51 +02:00
github-actions[bot] b75959f1f2 Bump version 2023-09-05 00:14:21 +00:00
Martin Povišer c6566b660f memlib.md: Fix typo 2023-09-04 17:38:35 +02:00
Martin Povišer 3de84b959f memory_libmap: Tweak whitespace 2023-09-04 17:38:35 +02:00
github-actions[bot] 73cb4977b2 Bump version 2023-09-02 00:14:04 +00:00
Miodrag Milanovic 72bec94ef4 Add missing file for XO3D 2023-09-01 10:15:51 +02:00
github-actions[bot] b739213d9f Bump version 2023-08-30 00:14:38 +00:00
Miodrag Milanović 51ddfb1f8e
Merge pull request #3909 from YosysHQ/widelut 
Default nowidelut for xo2/3/3d
 2023-08-29 11:04:49 +02:00
Miodrag Milanovic a42c630264 put back previous test state, due to default change 2023-08-29 10:21:58 +02:00
Miodrag Milanovic 792cf8326e defult nowidelut for xo2/3/3d 2023-08-29 10:08:55 +02:00
github-actions[bot] 572ad341b7 Bump version 2023-08-29 00:14:35 +00:00
Miodrag Milanovic b168ff99d0 fix generated blackboxes for ecp5 2023-08-28 16:26:26 +02:00
Jannis Harder 2f82e8eaed
Merge pull request #3906 from DanielG/fix-fstGetUint32-mips64el 2023-08-28 16:11:53 +02:00
github-actions[bot] 2f901a8297 Bump version 2023-08-28 00:15:18 +00:00
Daniel Gröber e4189ddfd1 Fix fstGetUint32 crash on mips64el due to misaligned access 
See https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1025307
 2023-08-27 15:05:41 +02:00
Jannis Harder 86df114a33
Merge pull request #3904 from DanielG/fix-fst-i386 2023-08-27 12:14:17 +02:00
Daniel Gröber e017f6603c Fix i386 FP excess-precision issue in fstapi (Fixes: #3898) 
Likely related to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=323#c225

Thanks to @jix for digging this up
 2023-08-27 11:32:53 +02:00
github-actions[bot] de54cf1a0c Bump version 2023-08-26 00:13:58 +00:00
Miodrag Milanović c6caadfed4
Merge pull request #3902 from YosysHQ/krys/yw_join 
yosys-witness concat yw trace files
 2023-08-25 15:21:44 +02:00
Miodrag Milanović 1b6d803877
Merge pull request #3900 from YosysHQ/micko/synth_lattice 
Create unified synth_lattice
 2023-08-25 12:44:30 +02:00
Miodrag Milanovic 0756285710 enable more primitives supported with nextpnr 2023-08-25 11:45:25 +02:00
Miodrag Milanovic 3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic 541c1ab567 add script for blackbox extraction 2023-08-23 11:51:00 +02:00
Miodrag Milanovic ea50d96135 fixed tests 2023-08-23 10:54:29 +02:00
Miodrag Milanovic 75fd706487 delete machxo2 since it is now supported in lattice 2023-08-23 10:54:17 +02:00
Miodrag Milanovic e3c15f003e Create synth_lattice 2023-08-23 10:53:21 +02:00
Miodrag Milanovic a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
github-actions[bot] 6405bbab1e Bump version 2023-08-18 00:14:07 +00:00
Asherah Connor 4a475fa7a2 cxxrtl: include iostream when prints are used 2023-08-17 07:08:22 +02:00
github-actions[bot] cbd3ff2d3a Bump version 2023-08-15 00:14:23 +00:00
Miodrag Milanović 316200493e
Merge pull request #3889 from povik/cellaigs-fix-gcc9-build 
cellaigs: Drop initializer list in call to `IdString::in`
 2023-08-14 16:05:57 +02:00
Martin Povišer 6d9cd16fad cellaigs: Drop initializer list in call to `IdString::in` 
Remove superfluous curly braces in call to IdString::in to address
a compilation error (reproduced below) under GCC 9 and earlier.

kernel/cellaigs.cc:395:18: error: call to member function 'in' is ambiguous
if (cell->type.in({ID($gt), ID($ge)}))
~~~~~~~~~~~^~
./kernel/rtlil.h:383:8: note: candidate function
bool in(const std::string &rhs) const { return *this == rhs; }
^
./kernel/rtlil.h:384:8: note: candidate function
bool in(const pool &rhs) const { return rhs.co...
^
 2023-08-14 11:42:19 +02:00
github-actions[bot] 008b725c1d Bump version 2023-08-13 00:15:02 +00:00
Charlotte 860e3e4056 proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
Charlotte bf84861fc2 proc_clean: only consider fully-defined case operands. 2023-08-12 02:46:31 +02:00
github-actions[bot] 40978971f4 Bump version 2023-08-12 00:13:32 +00:00
Charlotte 2829cd9caa cxxrtl_backend: move sync $print grouping out of dump into analyze 2023-08-11 04:46:52 +02:00
Charlotte ce245b5105 cxxrtl_backend: respect sync `$print` priority 
We add a new flow graph node type, PRINT_SYNC, as they don't get handled
with regular CELL_EVALs.  We could probably move this grouping out of
the dump method.
 2023-08-11 04:46:52 +02:00
Charlotte 04582f2fb7 verilog_backend: emit sync `$print` cells with same triggers together 
Sort by PRIORITY, ensuring output order.
 2023-08-11 04:46:52 +02:00